Multilevel Via Placement via R-Stack Segmentation for Electromigration
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Solution Overview
Problem
Integrated circuits with multiple levels of interconnects face reliability issues due to electromigration, particularly in via plugs where atomic flux divergence leads to stress-related failures, limiting current capacity and causing interconnect failures.
Innovation Solution
A computer system optimizes via placement by forming 'R-stack' structures where top and bottom vias are aligned within a specific distance, and prioritizes via placement based on current density to reduce electromigration risks, using redundant vias where necessary to distribute current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant vias are added to reduce current density and improve electromigration reliability, then via electromigration resistance is improved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The via structure is segmented into multiple levels (first level vias connecting second level interconnect to third level interconnect, and second level vias connecting third level interconnect to fourth level interconnect). This segmentation allows current to be distributed across multiple discrete via structures rather than overloading a single via, thereby improving electromigration resistance while maintaining manageable complexity through systematic organization.
Solution Approach 2:
The patent transitions from planar via placement to three-dimensional stacked via structures (R-stacks) where vias are vertically aligned across multiple interconnect levels. This dimensional transition allows redundant current paths to be formed in the vertical dimension, improving electromigration reliability without increasing lateral device footprint or overall structural complexity.
2Reliability
If via placement is optimized to improve electromigration reliability through R-stack formation, then manufacturing precision requirements increase, but via electromigration resistance improves
Solution Approach 1:
The patent establishes predetermined alignment rules for via placement before manufacturing, where first level vias and second level vias are pre-positioned to form R-stack structures with specific vertical alignment relationships. This preliminary action defines the geometric constraints and alignment tolerances in advance, allowing manufacturing processes to follow established patterns rather than requiring complex real-time precision control.
Solution Approach 2:
The patent modifies the via placement parameters by introducing vertical offset distances between first level vias and second level vias within the R-stack structure. By changing the spatial parameters from direct vertical alignment to controlled offsets, the design accommodates manufacturing variations while maintaining electromagnetic performance, thereby reducing the stringency of precision requirements.
3Reliability
If multilevel interconnect structures are implemented to reduce interconnect resistance, then electrical performance is improved, but electromigration reliability deteriorates due to increased current density in via plugs
Solution Approach 1:
The patent introduces intermediate via structures (first level vias and second level vias) that act as mediators between lower and upper interconnect levels. These intermediate vias distribute the current flow across multiple discrete conductive paths rather than concentrating it in single via plugs, thereby maintaining the low-resistance benefit of multilevel interconnect while mitigating electromigration through current density distribution.
Solution Approach 2:
The current path is segmented into multiple discrete via structures organized in R-stack configurations. By dividing the current carrying function across multiple segmented via elements rather than using monolithic via plugs, the patent reduces the current density in each individual via, thereby improving electromigration resistance while maintaining overall low interconnect resistance through the parallel conductive paths.
Data Source
AI summary
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.