Multi-Level Video PHY Coding for Longer HDMI Links

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Solution Overview

Problem

Current high-definition media interface (HDMI) technologies face limitations in extending cabling length and bandwidth for high-definition television signals, as existing solutions like TMDS and PAM systems either lack sufficient bandwidth or introduce significant processing overhead.

Innovation Solution

A new physical layer using multiple levels per symbol with a relatively low symbol clock rate, replacing TMDS, which includes a clock channel and data channels transmitting blocks of multi-level symbols, encoded and decoded using an 8/2/1B:3U encoding scheme, allowing for efficient transmission over twisted wire pairs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If TMDS (8B:10B) coding is used to transmit high-speed serial data, then bandwidth and data transmission rate are improved, but cabling length and electromagnetic interference resistance deteriorate

Engineering Contradiction:
Improvedata transmission rateVSAvoidelectromagnetic interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the fundamental parameter of signal encoding from binary (2-level) to quaternary (4-level) symbols. Each 4-level symbol carries 2 bits of information, allowing the system to transmit data at lower symbol rates while achieving the same effective bandwidth. This parameter change reduces the high-frequency content of the signal, thereby reducing electromagnetic interference and allowing for longer cable lengths without significant signal degradation

Inventive Principle:
Principle #35Parameter changes

2Length of stationary object

If multi-level symbols are used to extend cabling length, then electromagnetic interference is reduced, but processing overhead increases

Engineering Contradiction:
Improvecabling lengthVSAvoidprocessing overhead
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing DC balancing and transition minimization during the encoding phase before transmission. The encoder proactively adjusts the symbol sequence to maintain DC balance and minimize transitions, rather than requiring complex post-processing at the receiver. This preliminary processing simplifies the overall system complexity while enabling multi-level symbol transmission over longer cables

Inventive Principle:
Principle #10Preliminary action

3Productivity

If higher symbol rates are used to increase bandwidth, then data transmission capacity is improved, but signal integrity and cable length limitations worsen

Engineering Contradiction:
ImprovebandwidthVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from a one-dimensional binary signaling system to a two-dimensional quaternary symbol system. By utilizing four distinct voltage levels (or symbol states) instead of two, the system effectively adds an dimension to the signal space. This allows 2 bits of information to be encoded in a single symbol period, doubling the information density per symbol while maintaining the same physical bandwidth and symbol rate, thereby preserving signal integrity over longer distances

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8798189B2Digital video physical layer using a multi-level data code
Publication Date: 2014.08.05 CRESTRON ELECTRONICS INC
  • US8798189B2 patent drawing
  • US8798189B2 patent drawing
  • US8798189B2 patent drawing

AI summary

A system for communicating data comprises a clock channel configured to transmit a clock signal at a predetermined rate and at least one data channel configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate. Each block of multi-level symbols comprises a sequence of at least three multi-level symbols. Each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two. The fixed multiple of the clock rate is an integer greater than one.