Multi-Level Voltage Detection Using One Comparator
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Solution Overview
Problem
Existing voltage detector circuits, such as flash ADC and SAR ADC designs, face challenges in terms of speed, accuracy, power consumption, and complexity, particularly when tracking multi-level voltage signals.
Innovation Solution
A voltage detector circuit is proposed that includes a resistor divider circuit with N intermediate nodes, a switching circuit with N switches, a single comparator, a state machine, and a decoder. The state machine updates its state based on the comparator output, and the decoder activates the appropriate switches to track the voltage signal efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a flash ADC with multiple comparators is used for voltage detection, then voltage tracking speed is improved, but device area and power consumption increase significantly
Solution Approach 1:
The voltage detection range is segmented into multiple levels using a resistor divider circuit with N dividers creating N-1 intermediate nodes. A single comparator sequentially compares the input voltage against these segmented reference levels, achieving multi-level detection without requiring multiple parallel comparators, thus reducing device area while maintaining tracking speed
Solution Approach 2:
The voltage detector uses periodic clocked operation where the single comparator is activated in sequence for each voltage level comparison during each clock cycle. This periodic activation allows one comparator to perform the work of multiple comparators over time, reducing the number of comparators needed from N to 1 while maintaining the same detection functionality
2Speed
If a flash ADC with multiple comparators is used for voltage detection, then voltage tracking speed is improved, but power consumption increases
Solution Approach 1:
The voltage detection range is segmented into multiple levels using a resistor divider circuit with N dividers creating N-1 intermediate nodes. A single comparator sequentially compares the input voltage against these segmented reference levels, achieving multi-level detection without requiring multiple parallel comparators, thus reducing device area while maintaining tracking speed
Solution Approach 2:
The voltage detector uses periodic clocked operation where the single comparator is activated in sequence for each voltage level comparison during each clock cycle. This periodic activation allows one comparator to perform the work of multiple comparators over time, reducing the number of comparators needed from N to 1 while maintaining the same detection functionality
3Measurement precision
If the number of comparators is increased in a flash ADC, then voltage detection accuracy is improved, but parasitic load capacitance increases and limits operating speed
Solution Approach 1:
The voltage detection range is segmented into multiple levels using a resistor divider circuit with N dividers creating N-1 intermediate nodes. A single comparator sequentially compares the input voltage against these segmented reference levels, achieving multi-level detection without requiring multiple parallel comparators, thus reducing device area while maintaining tracking speed
Solution Approach 2:
Instead of using multiple physical comparators, the invention uses a single comparator that is time-multiplexed to perform multiple comparison functions. The same comparator is reused for each voltage level comparison in sequence, creating a functional copy of the comparison operation without duplicating the physical comparator hardware, thus reducing parasitic capacitance
4Use of energy by stationary object
If a SAR ADC with a single comparator is used, then power consumption and device area are reduced, but conversion speed decreases due to binary search algorithm
Solution Approach 1:
The resistor divider circuit pre-generates N-1 reference voltage levels at intermediate nodes before the comparison process begins. This preliminary preparation of reference levels allows the single comparator to directly compare against pre-established thresholds without requiring iterative binary search, enabling faster voltage detection in a single clock cycle while maintaining low power consumption
Solution Approach 2:
The voltage detector uses periodic clocked operation where the single comparator is activated in sequence for each voltage level comparison during each clock cycle. This periodic activation allows one comparator to perform the work of multiple comparators over time, reducing the number of comparators needed from N to 1 while maintaining the same detection functionality
Data Source
AI summary
In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.