Multilevel Wiring Scribe Structure for Low-k Dicing Crack Suppression
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Solution Overview
Problem
Low-k insulating films used in semiconductor devices, such as DRAM, have lower adhesion and are brittle, leading to crack propagation during dicing, which reduces yield and damages the main circuit portion.
Innovation Solution
A stacked structure is formed with metal wiring layers and low-k insulating films, and laser grooving is used to remove these layers in the dicing region, along with a photomask that controls photoresist thickness to prevent crack propagation, and the insulating films are etched with different thicknesses to reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k insulating films are used to reduce capacitance between interconnects, then high-speed operation is achieved, but cracks propagate during dicing reducing yield
Solution Approach 1:
The patent introduces scribe lines that divide the semiconductor wafer into individual chip regions. These scribe lines are positioned to interrupt crack propagation paths, segmenting the continuous low-k insulating film into isolated sections that cannot transmit cracks across chip boundaries during dicing operations.
Solution Approach 2:
The patent introduces a sacrificial layer positioned between the low-k insulating film and the substrate. This intermediary layer absorbs stress and prevents direct crack transmission from the brittle low-k film to the underlying circuit structures during dicing, while being removable afterward to restore full functionality.
2Speed
If low-k insulating films are used to reduce capacitance, then high-speed operation is achieved, but adhesion is reduced making the film brittle
Solution Approach 1:
The patent creates a composite structure combining the low-k insulating film with a sacrificial layer having different mechanical properties. This composite configuration allows the low-k film to maintain its low dielectric constant for high-speed operation while the sacrificial layer provides enhanced adhesion and crack resistance.
Solution Approach 2:
The sacrificial layer is positioned beforehand between the low-k insulating film and substrate to cushion against mechanical stresses during dicing. This pre-positioned protective layer absorbs impact and prevents stress concentration at the film-substrate interface before cracking can occur.
3Reliability
If laser grooving is used to remove metal wiring layers and insulating films in the dicing region, then crack propagation is suppressed, but manufacturing complexity increases
Solution Approach 1:
The patent performs laser grooving to create separation grooves in the metal wiring layers and insulating films before the actual dicing operation. This preliminary action pre-defines the separation paths and removes material that would otherwise be prone to cracking, simplifying the subsequent dicing process and reducing the need for complex crack management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses crack propagation during dicing, protecting the main circuit portions and improving the yield of semiconductor devices by reducing stress and ensuring precise control over photoresist and insulating film thickness.
Implementation Method 1
laser grooving is used to remove these layers in the dicing region
Implementation Method 2
a photomask that controls photoresist thickness to prevent crack propagation
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer.