Multiloop PLL Clock Recovery for Jitter and Wander Suppression
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Solution Overview
Problem
Conventional PLL circuits face challenges in simultaneously suppressing high-frequency jitter and low-frequency wander components in SDH signals reproduced from OTN signals, leading to increased costs and phase errors due to the need for large circuit scales and multiple-stage connections, which complicates the suppression of both components effectively.
Innovation Solution
A multiloop synthesizer configuration comprising three PLL units - one for high-frequency jitter suppression, one for low-frequency wander suppression, and one for reproduction clock, with each unit including frequency dividers, phase detectors, amplifiers, and VCOs, along with a phase monitor and amplifier controller to optimize amplifier gain constants based on phase state information, forming a small-scale incomplete integral type circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete integral type PLL circuit is used to suppress low-frequency wander component, then the low-frequency wander suppression is improved, but the circuit scale increases and cost increases
Solution Approach 1:
The patent divides the single PLL circuit into three separate PLL units with distinct functions: first PLL for high-frequency jitter suppression, second PLL for low-frequency wander suppression, and third PLL for reproduction clock generation. This segmentation allows each unit to be optimized for its specific frequency range, achieving effective wander suppression without requiring a large-scale complete integral type circuit.
2Reliability
If the phase noise cutoff frequency is set low (0.1 Hz to 1 Hz) to suppress low-frequency wander, then the wander suppression is improved, but the phase error increases
Solution Approach 1:
The patent segments the frequency suppression tasks between different PLL units. The first PLL handles high-frequency jitter with higher bandwidth, while the second PLL handles low-frequency wander with lower cutoff frequency (0.1-1 Hz). This segmentation allows the wander suppression PLL to operate at low cutoff frequency without excessively increasing phase error, as the high-frequency phase errors are already handled by the first PLL.
Solution Approach 2:
The first PLL unit acts as an intermediary that pre-processes the input signal by suppressing high-frequency jitter before passing it to the second PLL. This intermediary function reduces the burden on the second PLL, allowing it to focus on low-frequency wander suppression with lower cutoff frequency while maintaining acceptable phase error performance.
3Reliability
If multiple-stage PLL circuits are connected to suppress both high-frequency jitter and low-frequency wander, then the suppression performance is improved, but the phase errors are superposed and increase
Solution Approach 1:
The patent employs feedback mechanisms within each PLL unit and uses the output of one PLL as input to the next, creating a cascaded feedback system. The phase detectors in each unit continuously monitor phase differences and adjust their respective VCOs, ensuring that phase errors are corrected at each stage rather than accumulating. The amplifier controller further optimizes amplifier gain constants based on phase state information, actively managing phase error propagation.
Solution Approach 2:
The patent changes key parameters between different PLL units: the first PLL operates with higher bandwidth for jitter suppression, while the second PLL uses lower cutoff frequency for wander suppression. The amplifier gain constants are dynamically adjusted based on phase state information. These parameter changes allow each stage to operate optimally for its specific function while minimizing overall phase error accumulation.
4Device complexity
If a single PLL circuit is used, then the circuit scale is reduced, but it cannot simultaneously suppress both high-frequency jitter and low-frequency wander
Solution Approach 1:
The patent segments the suppression functions into three specialized PLL units, each optimized for specific frequency ranges. This segmentation achieves comprehensive suppression of both high-frequency jitter and low-frequency wander while maintaining a relatively compact overall circuit scale, as each unit can be designed efficiently for its specific purpose rather than requiring one large circuit to handle all frequencies.
Solution Approach 2:
Each PLL unit serves multiple purposes: the first PLL suppresses high-frequency jitter and provides a cleaned signal to the second PLL, the second PLL suppresses low-frequency wander and provides signal to the third PLL, and the third PLL generates the final reproduction clock. This multi-functionality allows the system to achieve comprehensive suppression performance without requiring additional dedicated circuits for each function.
Data Source
AI summary
The present invention provides a circuit, a control system, an IC, a transmitting and receiving apparatus, a control method, and a program which can reduce a phase error and simultaneously suppress a high-frequency jitter component and a low-frequency wander component. A PLL1 unit which is a high-frequency jitter suppression unit, a PLL2 unit which is a low-frequency wander suppression unit, and a PLL3 unit which is a reproduction clock unit are connected to form a multiloop synthesizer configuration.