Multi-Material Channel Layers for Etch-Resistant FinFETs

Solution Overview

Problem

The reduction in size of planar metal oxide semiconductor FETs in semiconductor devices with fine patterns leads to performance reductions due to increased channel layer loss during manufacturing.

Innovation Solution

A semiconductor device is designed with a three-dimensional channel structure, such as a FinFET, where the uppermost channel layer includes a material different from the lower channel layers to enhance etch resistance and reduce channel layer loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the size of planar metal oxide semiconductor FETs is reduced to achieve fine patterns, then the integration density increases, but the channel layer loss increases leading to performance reduction

Engineering Contradiction:

Improvedevice sizeVSAvoidchannel layer loss

Core Design Contradiction:

Area of moving objectVSLoss of substance

Solution Approach 1:

The patent applies local quality by making the uppermost channel layer have different material composition (higher silicon content) compared to the lower channel layers. This localized material differentiation enhances etch resistance specifically where needed (at the uppermost layer exposed to etching processes) while maintaining the overall multi-layer channel structure for high integration density.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by creating channel layers with varying silicon compositions (e.g., Si1-xGex where x varies). The uppermost layer has lower germanium content (higher silicon content) providing etch resistance, while lower layers have higher germanium content for other performance characteristics, forming a composite multi-layer structure that addresses both integration density and channel layer loss.

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If the channel layer thickness is reduced to achieve finer patterns, then the pattern resolution improves, but the channel layer loss during manufacturing increases

Engineering Contradiction:

Improvepattern resolutionVSAvoidchannel layer loss

Core Design Contradiction:

Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent applies local quality by making the uppermost channel layer have different material composition (higher silicon content) compared to the lower channel layers. This localized material differentiation enhances etch resistance specifically where needed (at the uppermost layer exposed to etching processes) while maintaining the overall multi-layer channel structure for high integration density.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies beforehand cushioning by designing the uppermost channel layer with enhanced etch resistance properties in advance, before the etching process occurs. This pre-engineered resistance acts as a protective cushion against the etching process, preventing excessive channel layer loss and maintaining pattern integrity during manufacturing.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the multi-layer channel structure is implemented to reduce channel layer loss, then the etch resistance improves, but the device complexity increases

Engineering Contradiction:

Improveetch resistanceVSAvoidchannel layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the uppermost channel layer have different material composition (higher silicon content) compared to the lower channel layers. This localized material differentiation enhances etch resistance specifically where needed (at the uppermost layer exposed to etching processes) while maintaining the overall multi-layer channel structure for high integration density.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies segmentation by dividing the channel structure into multiple layers with different material compositions. The channel is segmented into an uppermost layer with higher etch resistance and lower layers with different compositions, allowing each segment to perform its specific function while collectively providing improved reliability.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12224357B2Semiconductor transistor device including multiple channel layers with different materials

Publication Date: 2025.02.11 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.