Multimedia Application Processor Architecture for Parallel Signal Processing

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Solution Overview

Problem

Current application processor architectures can only process a single group of baseband signals, limiting their ability to handle multiple work tasks simultaneously, which affects processing efficiency and prevents devices from performing tasks like communication and other functions concurrently.

Innovation Solution

A multimedia application processor architecture featuring a master control system, multiple independent multimedia application processors, common CPUs, and a power manager, allowing for parallel processing of multiple baseband signals and tasks through dynamic resource allocation and power management, enabling simultaneous handling of multiple work tasks and requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single group of baseband signals is processed, then the processor architecture remains simple, but the device cannot handle multiple work tasks simultaneously

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidprocessor architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is divided into multiple independent MAP groups (first MAP group, second MAP group, etc.), each capable of independently processing a group of baseband signals. This segmentation allows parallel processing of multiple signal groups while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each MAP group is designed with universal functionality to process various types of signals including WiFi, GPS/BDS positioning, and 5G/6G modem signals. The common CPU groups provide backup processing capabilities that can be dynamically allocated to different MAP groups based on workload requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple independent MAP groups are added to process multiple baseband signals, then parallel processing capability improves, but power consumption increases

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system implements dynamic power management where the master control system monitors workload requirements and dynamically adjusts the operational state of each MAP group. When parallel processing is needed, multiple MAP groups are activated; when processing demand decreases, MAP groups are powered down or placed in low-power mode, optimizing power consumption based on actual needs

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Each MAP group includes its own CPU, GPU, audio processor, video encoder/decoder, and other processing units that can operate independently. This self-service capability allows individual MAP groups to handle their own processing tasks without requiring constant intervention from other groups, enabling more efficient power management

Inventive Principle:
Principle #25Self-service

3Reliability

If common CPU groups are added as backup processing resources, then processing reliability improves, but device complexity increases

Engineering Contradiction:
Improveprocessing reliabilityVSAvoidsystem configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The master control system serves as an intermediary that manages the allocation and coordination between independent MAP groups and common CPU groups. It monitors the processing status of each MAP group and dynamically requisitions common CPU groups when processing limits are reached, providing a centralized control mechanism that simplifies the complexity of managing multiple processing resources

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11455273B2Multimedia application processor architecture
Publication Date: 2022.09.27 ZHONG JIEDONG
  • US11455273B2 patent drawing

AI summary

This disclosure provides a multimedia application processor architecture, comprising a master control system, at least two groups of independent multimedia application processors, at least two groups of common CPU, a power manager, and a common interface and CPU bus, wherein the master control system is connected to each group of the independent multimedia application processors, each group of the common CPU, the power manager, and the common interface and CPU bus respectively, and is configured to control and manage, and provide power control and management for, the at least two groups of independent multimedia application processors, the at least two groups of common CPU, the power manager, and the common interface and CPU bus, each group of the common CPU is connected to the independent multimedia application processors for providing a backup central processor data processing capability for the independent multimedia application processors.