Multi-Modal Clock Recovery Using Composite Phase-Error Signals
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Clock and Data Recovery (CDR) methods face challenges in maintaining accurate clock recovery due to varying signal propagation conditions and noise interference, leading to instability and increased jitter in Phase-Locked Loops (PLLs).
Innovation Solution
The implementation of a data-driven phase comparator circuit that utilizes multiple partial phase comparators and a phase interpolator to generate a composite phase-error signal, enabling improved PLL lock characteristics and reduced circuit node capacitance, which enhances loop stability and power supply noise rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing Clock and Data Recovery (CDR) methods are used in high-speed chip-to-chip communication systems, then clock recovery can be achieved, but the system experiences instability and increased jitter in Phase-Locked Loops (PLLs) due to varying signal propagation conditions and noise interference
Solution Approach 1:
The phase comparator is divided into multiple partial phase comparators, each processing different portions of the input signals. This segmentation allows the system to handle varying signal propagation conditions more effectively by distributing the processing load and reducing the impact of noise and jitter on any single comparator.
Solution Approach 2:
Multiple partial phase-error signals from the segmented comparators are combined to form a composite phase-error signal. This merging process integrates the information from multiple sources, improving the reliability of clock recovery by averaging out noise and jitter effects while maintaining stability in varying propagation conditions.
2Stability of the object's composition
If traditional phase comparator circuits are used, then phase detection can be performed, but the circuit node capacitance is high which reduces loop stability and power supply noise rejection
Solution Approach 1:
The phase comparator circuit is segmented into multiple partial comparators with smaller individual capacitances. By dividing the total capacitance across multiple smaller units, the overall loop stability is improved while maintaining the necessary phase detection functionality. This segmentation reduces the capacitive load on the PLL, enhancing noise rejection.
Solution Approach 2:
Different regions of the phase comparator circuit are designed with optimized local characteristics. Each partial comparator is designed to contribute specifically to the composite signal with minimized local capacitance, allowing the overall system to achieve high stability and noise rejection while maintaining accurate phase detection across the full signal range.
3Measurement precision
If multiple partial phase comparators and a phase interpolator are implemented to generate a composite phase-error signal, then PLL lock characteristics are improved and loop lock bandwidth is increased, but the device complexity increases
Solution Approach 1:
The phase detection function is segmented into multiple partial comparators that can be implemented using standard cell libraries. This segmentation enables precise phase detection by distributing the measurement function across multiple simple units, improving precision without requiring a single complex comparator design.
Solution Approach 2:
The phase interpolator is designed to perform multiple functions: it combines partial phase-error signals, generates the composite phase-error signal, and provides phase adjustment for PLL locking. This multi-functionality reduces the need for separate dedicated circuits, thereby improving measurement precision while limiting the increase in overall device complexity.
Data Source
AI summary
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.