Multi-Modal Clock Recovery Circuit for Low-Jitter Phase Detection
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Clock and Data Recovery (CDR) methods face challenges in maintaining accurate clock recovery due to varying signal propagation conditions and noise interference, leading to instability and increased jitter in Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs.
Innovation Solution
A multi-modal data-driven clock recovery circuit is introduced, utilizing a data-driven phase comparator that processes multiple data signals in parallel from a multi-wire bus, generating partial phase-error signals and a composite phase-error signal to adjust the local oscillator phases, enhancing loop stability and reducing jitter through improved phase detection and interpolation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing Clock and Data Recovery methods are used in high-speed chip-to-chip communication systems, then clock recovery can be achieved, but loop stability deteriorates and jitter increases due to varying signal propagation conditions and noise interference
Solution Approach 1:
The patent segments the clock recovery process into multiple parallel data signal paths, where each path independently processes phase error detection. This segmentation allows the system to handle varying signal propagation conditions more robustly by distributing the recovery workload across multiple channels, thereby improving loop stability without increasing jitter.
Solution Approach 2:
The patent combines multiple partial phase-error signals from parallel data paths into a composite phase-error signal. This merging approach integrates information from multiple sources to create a more reliable control signal for the local oscillator, enhancing both loop stability and reducing jitter through diversified input data.
2Measurement precision
If Phase-Locked Loops and Delay-Locked Loops are used for clock recovery, then clock synchronization can be achieved, but the circuits exhibit increased sensitivity to power supply noise and reduced lock bandwidth
Solution Approach 1:
The patent implements a feedback mechanism where the composite phase-error signal continuously adjusts the local oscillator phases. This closed-loop feedback system dynamically compensates for power supply noise and maintains accurate phase detection, thereby reducing sensitivity to noise while preserving lock bandwidth through active correction.
Solution Approach 2:
The clock recovery circuit uses its own output signals to generate the control voltage for adjusting local oscillator phases. This self-service approach allows the system to autonomously correct phase errors without external intervention, improving noise rejection and maintaining detection accuracy through internal regulation.
3Measurement precision
If traditional phase comparator circuits are used, then phase error detection can be performed, but circuit node capacitance increases leading to reduced loop response speed
Solution Approach 1:
The patent extracts only the essential phase error information from multiple data signals without processing the entire signal spectrum. By taking out only the relevant phase comparison data and discarding redundant information, the circuit reduces node capacitance while maintaining detection precision, thereby improving loop response speed.
Solution Approach 2:
The patent performs partial phase error detection on selected data signals rather than processing all signals completely. This partial action approach reduces the computational and capacitive burden on the circuit while still providing sufficient phase error information for effective clock recovery, thus enhancing response speed without sacrificing necessary detection accuracy.
Data Source
AI summary
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.