Multi-Modal Memory Interface I/O Pad Capacitance Reduction

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Solution Overview

Problem

Multi-modal memory controllers face challenges in minimizing capacitance at I/O pads connected to multiple I/O drivers, which affects high-speed signaling performance due to incompatible voltage and swing levels between single-ended and differential memory systems.

Innovation Solution

The design of a multi-modal memory interface that couples different types of drivers to each I/O pad, such as sharing pull-down resistors between differential current-mode and single-ended voltage-mode drivers, and using near-ground signaling to reduce capacitance and optimize power consumption, allowing for bidirectional asymmetric signaling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple I/O drivers are connected to I/O pads to support both single-ended and differential signaling modes, then the memory controller can be compatible with various memory devices, but the capacitance at the I/O pads increases which degrades high-speed signaling performance

Engineering Contradiction:

Improvecompatibility with various memory devicesVSAvoidhigh-speed signaling performance

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the I/O pad structure by introducing separate pad structures for voltage-mode and current-mode drivers, with shared and dedicated portions. The I/O pad is divided into a shared pad region and driver-specific pad regions, allowing independent optimization of each driver type while maintaining compatibility with both single-ended and differential memory devices

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the functionality of multiple drivers by implementing a shared I/O pad infrastructure where voltage-mode and current-mode drivers share common pad structures and termination networks. This consolidation reduces the total capacitance compared to having completely separate pad structures for each driver type

Inventive Principle:

Principle #5Merging (Combining)

2Device complexity

If voltage-mode drivers are used for simple implementations, then the device complexity is reduced, but power consumption increases compared to current-mode drivers

Engineering Contradiction:

Improveimplementation complexityVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic mode selection capability where the memory controller can switch between voltage-mode and current-mode signaling based on the specific memory device being used and the performance requirements. This dynamic adaptability allows the system to optimize the trade-off between complexity and power consumption for each operating condition

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If current-mode drivers are used for complex implementations, then power consumption is reduced, but the device complexity and requirement for calibration circuitry increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcalibration and equalization circuitry

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent creates a universal I/O pad structure that can accommodate both voltage-mode and current-mode drivers with the same physical infrastructure. The shared pad design and common termination networks allow the system to use current-mode drivers for power-efficient operation without requiring separate dedicated hardware paths, reducing the overall complexity increase

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9471518B2Multi-modal memory interface

Publication Date: 2016.10.18 RAMBUS INC

AI summary

A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques.