Multimode CDR Circuit for Forwarded and Embedded Clock Links
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Solution Overview
Problem
Current systems require two versions of receiving circuits for handling embedded and forwarded clocks, increasing manufacturing costs and complexity due to the need for compatibility with different clock transmission schemes in high-speed serial links.
Innovation Solution
A bimodal serial link clock and data recovery system that can generate a local clock from either a forwarded clock or an embedded clock, utilizing a phase locked loop with a sampler, crossing sampler, and bang-bang phase detector, and includes a phase interpolator and control logic to switch between modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two versions of receiving circuits are provided for embedded clock and forwarded clock schemes, then compatibility with different clock transmission schemes is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The receiving circuit is designed with a single unified architecture that can operate in multiple modes: embedded clock mode, forwarded clock mode, and hybrid mode. The circuit uses mode selection logic and configurable components (such as selectable phase detectors and clock sources) to adapt its behavior based on the transmission scheme being used, eliminating the need for separate circuit versions while maintaining full compatibility with different clock transmission schemes
Solution Approach 2:
The receiving circuit incorporates dynamic configuration capabilities through mode selection logic that can switch between different operational modes based on the detected clock transmission scheme. The circuit dynamically adjusts its internal parameters and component configurations (such as enabling/disabling specific phase detection paths or clock sources) to optimize performance for the current mode, allowing a single circuit to replace multiple static versions
2Adaptability or versatility
If two versions of receiving circuits are provided for embedded clock and forwarded clock schemes, then compatibility with different clock transmission schemes is improved, but manufacturing cost increases
Solution Approach 1:
The receiving circuit is designed with a single unified architecture that can operate in multiple modes: embedded clock mode, forwarded clock mode, and hybrid mode. The circuit uses mode selection logic and configurable components (such as selectable phase detectors and clock sources) to adapt its behavior based on the transmission scheme being used, eliminating the need for separate circuit versions while maintaining full compatibility with different clock transmission schemes
Solution Approach 2:
The patent merges the functionality of separate embedded clock receiver and forwarded clock receiver circuits into a single integrated receiving circuit. By combining the clock recovery logic, phase detection mechanisms, and data sampling functions into one unified structure with mode-selectable pathways, the design achieves both compatibility with different schemes and manufacturing efficiency through standardized production of a single circuit type
3Device complexity
If a single receiving circuit is used for both embedded clock and forwarded clock schemes, then device complexity and manufacturing cost are reduced, but adaptability to different clock transmission schemes deteriorates
Solution Approach 1:
The receiving circuit incorporates dynamic configuration capabilities through mode selection logic that can switch between different operational modes based on the detected clock transmission scheme. The circuit dynamically adjusts its internal parameters and component configurations (such as enabling/disabling specific phase detection paths or clock sources) to optimize performance for the current mode, allowing a single circuit to replace multiple static versions
Data Source
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AI summary
A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.