Multimode Cryptographic Processor With Thread-Capable Security Block

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current general-purpose processors are inefficient in handling high-capacity network and storage workloads, and cryptographic operations consume significant resources, particularly in symmetric ciphers like AES, which can lead to performance bottlenecks in modern data centers.

Innovation Solution

A highly programmable data processing unit with specialized hardware accelerators, including a multistage AES pipeline and a thread-capable security block, is designed to perform multiple AES modes at high throughput rates, utilizing multiple threads for idle times to increase utilization and streamline cryptographic operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general-purpose processors are used to handle cryptographic operations, then versatility is maintained, but processing speed and resource efficiency deteriorate

Engineering Contradiction:

Improveprocessor versatilityVSAvoidcryptographic processing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The processor is segmented into multiple specialized execution units, each dedicated to specific cryptographic operations. These units include AES execution units for symmetric encryption, hash execution units for hashing operations, and asymmetric execution units for public-key cryptography. This segmentation allows simultaneous execution of different cryptographic algorithms without resource contention, resolving the contradiction between versatility and processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processor implements a universal cryptographic processing architecture that can execute multiple cryptographic algorithms through a single integrated design. The execution units are designed to handle various modes of operation (ECB, CBC, CTR, GCM for AES; SHA-1, SHA-2, SHA-3; RSA, ECC) within a unified framework, maintaining versatility while achieving high throughput through specialized hardware acceleration.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If a single AES pipeline is used, then device complexity is reduced, but throughput for feedback-based modes deteriorates

Engineering Contradiction:

Improvepipeline structure complexityVSAvoidAES throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The single AES pipeline is designed with continuous operation capability through sophisticated buffering and scheduling mechanisms. For feedback-based modes like CBC and CTR, the pipeline maintains continuous useful action by pre-fetching data, using double-buffering techniques, and implementing overlapping processing stages. This allows the pipeline to operate at full capacity without idle cycles, achieving high throughput for all AES modes despite the simplified single-pipeline structure.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary actions by pre-computing and buffering data before it reaches the AES pipeline. For feedback modes, initialization vectors and previous ciphertext blocks are prepared in advance and staged in buffers. Key expansion and other preprocessing operations are completed before the main encryption/decryption pipeline executes, ensuring the pipeline operates continuously at maximum efficiency.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If cryptographic operations are performed using software implementation, then adaptability is maintained, but resource consumption and processing time increase

Engineering Contradiction:

Improvealgorithm flexibilityVSAvoidcryptographic processing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The processor replaces software-based cryptographic operations with dedicated hardware execution units. Each cryptographic algorithm (AES, hash functions, asymmetric cryptography) has corresponding hardware units that perform operations in parallel with data flow processing. This substitution of mechanical/software operations with hardware acceleration dramatically reduces processing time while maintaining algorithm flexibility through programmable control logic that can select and configure different cryptographic operations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11405179B2Multimode cryptographic processor

Publication Date: 2022.08.02 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.