Multi-Mode Frequency Divider for Gap-Free PLL Frequency Coverage
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) face challenges in achieving a wide frequency range without sacrificing power and phase noise performance, particularly due to gaps in frequency coverage at higher frequencies, and existing solutions like multiple VCOs or divide-by-three frequency dividers are either inefficient or unsuitable for broad frequency ranges.
Innovation Solution
A configurable divide-by-two and divide-by-three multi-mode frequency divider with integrated circuitry and edge-combining and interpolation circuitry, allowing operation in either div2 or div3 mode, and featuring programmable capacitors for adaptive frequency handling, implemented as a CMOS device to reduce power consumption and eliminate frequency gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single VCO with limited tuning range is used, then power consumption and phase noise performance are maintained, but frequency coverage gaps occur at higher frequencies
Solution Approach 1:
The frequency divider dynamically switches between div2 and div3 modes based on the desired output frequency. The control logic selects div3 mode for frequencies in the 5.25-7 GHz range and div2 mode for other ranges, allowing a single VCO to cover the entire frequency spectrum without gaps while maintaining power efficiency
Solution Approach 2:
The invention changes the division ratio parameter from fixed (either 2 or 4) to variable (2 or 3). This parameter change allows the system to bridge the frequency gap by using div3 in the intermediate range, enabling continuous frequency coverage from the VCO's minimum to maximum tuning range without sacrificing power performance
2Adaptability or versatility
If multiple VCOs are used to cover different frequency ranges, then frequency coverage gaps are eliminated, but circuit overhead and size increase significantly
Solution Approach 1:
A single frequency divider circuit is designed to perform multiple functions by operating in different division modes (div2 and div3). This multi-functional approach eliminates the need for multiple separate VCOs and frequency divider circuits, reducing circuit overhead and size while maintaining comprehensive frequency coverage
Solution Approach 2:
The invention merges the functionality of multiple frequency dividers (div2 and div3) into a single integrated circuit. The control logic and switching mechanisms combine these functions, eliminating the need for separate circuits and reducing overall system complexity and component count
3Adaptability or versatility
If LC VCOs are used for each frequency range, then frequency coverage is improved, but PLL size increases due to multiple inductor coils
Solution Approach 1:
A single LC VCO is designed to operate across a wide tuning range, and the frequency divider provides multi-functional operation (div2/div3) to cover the entire spectrum. This eliminates the need for multiple LC VCOs with separate inductor coils, significantly reducing the PLL footprint while maintaining full frequency coverage
4Adaptability or versatility
If conventional div3 frequency divider is used, then frequency gap is bridged, but 50% duty cycle and quadrature phase are not achieved
Solution Approach 1:
An edge-combining circuit acts as an intermediary between the div3 frequency divider output and the final output. This circuit combines the edges of the divided signals and reconstructs the waveform to achieve the precise 50% duty cycle and quadrature phase relationships required, while still benefiting from the frequency bridging capability of div3 operation
Data Source
AI summary
A frequency divider includes first circuitry, second circuitry, and third circuitry. The first circuitry includes divide-by-two (div2) frequency divider circuitry, and the second circuitry includes additional circuitry for a divide-by-three (div3) frequency divider. The second circuitry is selectively enabled using a control signal and can receive signals from the first circuitry when enabled. Specifically, the second circuitry is enabled in the div3 mode but is not enabled in the div2 mode. The third circuitry receives signals from the first circuitry and also receives signals from the second circuitry when the second circuitry is enabled. The first circuitry and the third circuitry function as a div2 frequency divider when the second circuitry is not enabled. The first circuitry, the second circuitry, and the third circuitry function as a div3 frequency divider when the second circuitry is enabled.


