Multi-Mode LDPC Coding for Hard- and Soft-Decision PON Receivers

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Solution Overview

Problem

Passive optical networks (PON) face challenges in efficiently supporting high-speed transmission rates due to the need for separate hardware configurations for hard-decision and soft-decision receivers, leading to increased complexity and reduced performance at higher data rates like 50 Gbit/s.

Innovation Solution

The implementation of a multi-mode Low-Density Parity-Check (LDPC) encoder and decoder that can optimize code matrices for both hard and soft input channels using the same hardware, allowing for re-use of circuitry and reduced complexity by modifying parity-check matrices through puncturing and column swapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate hardware configurations are used for hard-decision and soft-decision receivers, then receiver performance is optimized for specific modes, but device complexity increases

Engineering Contradiction:
Improvereceiver performanceVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal LDPC encoder and decoder that can operate in both hard-decision and soft-decision modes using the same hardware circuitry. The encoder uses a single parity-check matrix that can be configured for different modes, and the decoder can process both hard-decision inputs (0/1 values) and soft-decision inputs (log-likelihood ratio values), eliminating the need for separate hardware configurations for each receiver type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple FEC settings are implemented for different receiver architectures, then adaptability to different modes is improved, but device complexity increases

Engineering Contradiction:
Improvemulti-mode supportVSAvoidFEC configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs dynamic configuration of the LDPC encoder and decoder where the same hardware can be reconfigured between hard-decision and soft-decision modes through control signals. The encoder can switch between using the full parity-check matrix or punctured versions, and the decoder can dynamically adjust its processing based on whether it receives hard-decision or soft-decision inputs, allowing multi-mode support without multiple fixed hardware configurations.

Inventive Principle:
Principle #15Dynamics

3Productivity

If transmission speed is increased to 50 Gbit/s, then productivity is improved, but signal transmission quality deteriorates

Engineering Contradiction:
Improvedata rateVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies forward error correction using LDPC codes to combat signal degradation at high transmission rates. By using sophisticated error correction algorithms with configurable parity-check matrices, the system can maintain signal quality and reduce bit error rates even at 50 Gbit/s transmission speeds, where signal quality would naturally deteriorate without such correction mechanisms.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11876622B2LDPC encoder and decoder for multi-mode higher speed passive optical networks
Publication Date: 2024.01.16 INTEL CORP
  • US11876622B2 patent drawing
  • US11876622B2 patent drawing
  • US11876622B2 patent drawing

AI summary

Examples relate to a Forward Error Correction (FEC) encoder, an FEC decoder, Passive Optical Network (PON) systems, an Optical Line Terminal (OLT), an Optical Networking Unit (ONU), and to corresponding methods and computer programs. A forward-error-correction (FEC) encoder that is suitable for generating FEC data for use with hard-decision input at a receiver and for use with soft-decision input at the receiver is configured to generate the FEC data based on payload bits using a Low-Density Parity-Check (LDPC) code. The generated FEC data is generated using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver or using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively.