Multi-Mode Logic Block with Shared Output to Cut PLD Routing Delay
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Solution Overview
Problem
Existing programmable logic devices face challenges in providing multiple modes while minimizing delay and routing complexity, particularly in logic blocks that support combinational modes.
Innovation Solution
The implementation of a logic block with combined outputs, including a first and second LUT circuit, a ripple logic circuit, and a three-to-one multiplexer circuit, which allows for selective operation in LUT or ripple modes, reducing intermediate components and optimizing performance and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic blocks support multiple combinational modes with multiple output ports, then functionality and adaptability are improved, but delay and routing complexity increase
Solution Approach 1:
The patent combines multiple output ports into a single shared output port for logic blocks supporting multiple combinational modes (LUT mode and ripple mode). Instead of providing separate output ports for each mode, the invention uses a single output port that can be configured to carry signals from either mode, thereby reducing routing complexity while maintaining multi-mode functionality.
Solution Approach 2:
The single output port is designed to serve multiple functions by supporting both LUT mode and ripple mode operations. The output port can be dynamically configured or selected to carry different types of signals depending on the operational mode, making it a universal interface that replaces multiple specialized ports.
2Adaptability or versatility
If logic blocks support multiple combinational modes with multiple output ports, then functionality and adaptability are improved, but delay increases
Solution Approach 1:
By merging the output paths of LUT mode and ripple mode into a single shared output port, the patent eliminates the need for additional multiplexing stages and intermediate buffering that would increase delay. The direct connection to a single output port reduces the number of logic stages signals must traverse.
Solution Approach 2:
The invention extracts and removes intermediate multiplexers and buffer components that would be necessary if separate output ports were used for each mode. By taking out these intermediate elements, the signal path is shortened and delay is reduced while still supporting multiple modes through the single output port.
3Adaptability or versatility
If logic blocks support multiple combinational modes with multiple output ports, then functionality is improved, but area and cost increase
Solution Approach 1:
The patent merges the output infrastructure for multiple modes into a single shared output port, eliminating the need for duplicate output buffers, multiplexers, and associated routing resources. This consolidation significantly reduces the area occupied by output circuitry within each logic block while maintaining the ability to support both LUT and ripple modes.
Data Source
AI summary
Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.