Multi-Mode PE Array for Matrix Multiply and Convolution Switching
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Solution Overview
Problem
Existing systems struggle to efficiently perform matrix multiplication, 1x1 convolution, and 3x3 convolution due to inefficiencies in computation speed and power consumption, particularly in specialized tasks like transformer architectures and object detection in autonomous driving.
Innovation Solution
A system with control logic and a processing element array that can switch between modes to perform matrix multiplication, 1x1 convolution, and 3x3 convolution, utilizing a first and second buffer to store arrays from memory and processing elements that compute dot products in clock cycles, optimizing for speed and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware architectures are used for matrix multiplication, 1x1 convolution, and 3x3 convolution, then each operation can be optimized for its specific function, but the device complexity increases and power consumption rises
Solution Approach 1:
The patent implements a unified processing element that can perform matrix multiplication, 1x1 convolution, and 3x3 convolution using the same hardware architecture. The processing element array is designed to accept different input configurations and control signals to execute different operations, eliminating the need for separate dedicated hardware for each operation type while maintaining optimization for each specific function
Solution Approach 2:
The system employs dynamic configuration of the processing element array through control logic that adjusts the operation mode based on the required computation. The same physical hardware can be reconfigured between different convolution types and matrix multiplication through control signals, allowing adaptive switching between operations without physical reconfiguration
2Reliability
If separate hardware architectures are used for matrix multiplication, 1x1 convolution, and 3x3 convolution, then each operation can be optimized for its specific function, but power consumption increases
Solution Approach 1:
By using a single unified processing element array to perform all three operations (matrix multiplication, 1x1 convolution, and 3x3 convolution), the system eliminates the power overhead of maintaining multiple separate hardware architectures. The same physical processing elements are reused across different operations, significantly reducing overall power consumption while maintaining operational accuracy
Solution Approach 2:
The patent merges the functionality of separate computation units into a single integrated processing element array. By combining matrix multiplication and different convolution operations into one shared hardware resource, the system reduces redundant power consumption that would occur with separate dedicated units for each operation type
3Productivity
If traditional systems perform matrix multiplication and convolutions, then computational tasks are completed, but computational overhead and processing time are excessive
Solution Approach 1:
The patent segments the computation into parallel dot product operations performed by multiple processing elements simultaneously. Each processing element computes a portion of the result in parallel, significantly reducing the overall processing time compared to sequential computation. The segmentation of input data into manageable chunks that can be processed concurrently by the processing element array enables high-speed computation
Solution Approach 2:
The system maintains continuous computation by keeping the processing element array actively engaged throughout the calculation process. Data is fed continuously into the processing elements, and results are generated in a continuous stream, eliminating idle time and maximizing computational throughput. The pipelined architecture ensures that useful computation occurs at every clock cycle
Data Source
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AI summary
In a system with control logic and a processing element array, two modes of operation may be provided. In the first mode of operation, the control logic may configure the system to perform matrix multiplication or 1x1 convolution. In the second mode of operation, the control logic may configure the system to perform 3x3 convolution. The processing element array may include an array of processing elements. Each of the processing elements may be configured to compute the dot product of two vectors in a single clock cycle, and further may accumulate the dot products that are sequentially computed over time.