Multimode RS FEC Encoding for Dynamic Power Control
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Solution Overview
Problem
Conventional methods for high-speed communications links often result in unnecessary power consumption due to the inability to dynamically adjust the Reed-Solomon (RS) FEC code pattern, leading to excessive error correction capability for most links, which is not required.
Innovation Solution
A multimode RS FEC encoder and decoder system that dynamically adjusts its operating modes by enabling only necessary encoding units, allowing incremental encoding and decoding, thereby reducing power consumption and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the strongest FEC algorithm is chosen for poorest links, then bit error performance is improved, but power consumption increases due to unnecessary error correction capability
Solution Approach 1:
The patent implements dynamic adjustment of FEC code patterns based on link quality conditions. The system can switch between different RS code configurations (e.g., RS(255,223), RS(255,221), RS(255,219)) according to actual channel conditions, enabling the error correction capability to match the required level rather than always using the strongest algorithm. This dynamic adaptation resolves the contradiction by activating strong error correction only when link quality degrades, reducing unnecessary power consumption during normal operation while maintaining bit error performance when needed.
Solution Approach 2:
The patent changes the parameters of the FEC code pattern (specifically the code length and redundancy) based on link quality. By adjusting the code rate and redundancy levels dynamically, the system optimizes the balance between error correction capability and computational power consumption. This parameter adaptation allows the system to use minimal necessary error correction resources for good links while providing enhanced protection for poor links, resolving the technical contradiction.
2Reliability
If a fixed strong FEC algorithm is used, then error correction capability is maximized, but device complexity increases due to inability to dynamically adjust
Solution Approach 1:
The patent introduces dynamic configurability to the FEC system, allowing the code pattern to be adjusted based on link quality feedback. The system maintains multiple RS code configurations and can dynamically select and switch between them, transforming a static complex system into a dynamic adaptive one. This resolves the contradiction by making the error correction capability adjustable rather than fixed, reducing complexity through selective activation of only necessary code patterns.
Solution Approach 2:
The patent segments the FEC capability into multiple discrete code pattern options (different RS codes with varying redundancy levels). Instead of implementing a single monolithic strong FEC algorithm, the system divides the error correction capability into modular segments that can be independently activated. This segmentation reduces overall device complexity by allowing selective deployment of only the required error correction strength for each link condition.
Data Source
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AI summary
An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N0, K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (Nj, K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D0(x) and a remainder R0(x) of xN0-Km(x) relative to g0(x). An (h+1)th incremental encoding unit is configured to obtain, according to a quotient Dh(x) and a remainder Rh(x), a quotient Dh+1(x) and a remainder Rh+1(x) of xNh+1-Km(x) relative to gh+1(x).