Multipath Bootstrap Sampling Circuit for High-Frequency Linearity

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Solution Overview

Problem

Conventional bootstrapped ADC circuits exhibit non-linearity at high frequencies due to parasitic capacitance from high fan-out connections and bulk transistor connections, limiting their performance in high-speed and high-accuracy applications.

Innovation Solution

A multipath bootstrapped sampling circuit is introduced, featuring a primary bootstrap path driving only the gate terminal of the sampling transistor and auxiliary paths driving other transistors, along with multiple bootstrap capacitors to minimize parasitic capacitance, allowing optimal clock driver configuration and capacitance distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional bootstrapped ADC circuits use high fan-out connections and bulk transistor connections, then the circuit can be implemented with standard connections, but parasitic capacitance increases causing non-linearity at high frequencies

Engineering Contradiction:
ImprovelinearityVSAvoidparasitic capacitance
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The bootstrap path is segmented into multiple independent paths: a primary bootstrap path with minimal fan-out connecting only essential nodes, and auxiliary bootstrap paths handling other transistor gates. This segmentation isolates the critical sampling transistor bootstrap connection from parasitic capacitance sources while still providing complete bootstrapping functionality for all transistors.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the primary bootstrap path drives multiple transistors (high fan-out), then the circuit implementation is simplified, but the linearity degrades due to increased parasitic capacitance

Engineering Contradiction:
Improvecircuit implementationVSAvoidlinearity
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The bootstrap function is divided between primary and auxiliary paths. The primary path is minimized to drive only the sampling transistor gate, ensuring low parasitic capacitance and high linearity. Auxiliary paths handle bootstrapping of other transistors, distributing the implementation complexity away from the critical sampling path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Auxiliary bootstrap paths act as intermediaries that provide bootstrapping signals to transistors that would otherwise require connections through the primary bootstrap path. This mediation allows the primary path to remain minimal while still achieving complete bootstrapping of the circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the linearity and accuracy of the sampling transistor at very high frequencies, improving the overall performance of ADC circuits by reducing parasitic capacitance and optimizing transistor connections.

Implementation Method 1

two bootstrap capacitors... The first bootstrap capacitor is connected to a first bootstrap path that drives only one load: a gate terminal of the sampling transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10897263B1Multiple paths bootstrap configuration for sample and hold circuit
Publication Date: 2021.01.19 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US10897263B1 patent drawing
  • US10897263B1 patent drawing
  • US10897263B1 patent drawing

AI summary

A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path. Additional auxiliary bootstrap paths may be added, providing the opportunity to optimize each clock driver to a specific driven transistor. Additional bootstrap capacitors may be added, to distribute the capacitance among auxiliary bootstrap paths. The reduction in parasitic capacitance at the sampling transistor enhances its linearity, and hence accuracy, at very high frequencies.