Multipath Chopper Circuit With Asymmetric Clocking for Noise Folding

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Solution Overview

Problem

Multipath chopper amplifiers face performance limitations due to mismatch issues between different paths, leading to increased noise folding and reduced effective gain, particularly when chopping at high frequencies to avoid quantization noise folding.

Innovation Solution

A chopper circuit with multiple chopper devices in parallel circuit paths, each controlled by distinct clock signals with varying frequencies, where one path is chopped at a higher frequency than the others to minimize mismatches and reduce noise folding, ensuring one chopping edge in every sampling period.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If chopping is performed at high frequency (fs/2) to avoid quantization noise folding, then noise folding is reduced, but effective amplifier gain is reduced and thermal noise increases

Engineering Contradiction:
Improvequantization noise foldingVSAvoideffective amplifier gain
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The amplification process is divided into multiple parallel paths (first path, second path, third path) with different chopping frequencies. Each path processes the signal independently with its own chopper device, allowing the system to combine the benefits of different chopping frequencies while mitigating individual path limitations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different paths are assigned different chopping frequencies tailored to their specific functions. The first path uses fs/2 for noise folding avoidance, while the second and third paths use lower frequencies to maintain gain and reduce thermal noise. This localized optimization resolves the contradiction by applying different frequency strategies to different signal processing paths.

Inventive Principle:
Principle #3Local quality

2Reliability

If multipath chopping is used to improve chopping artifacts, then performance is improved, but mismatch between paths increases

Engineering Contradiction:
Improvechopping artifact performanceVSAvoidpath matching
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent deliberately uses asymmetric chopping frequencies across paths (fs/2 for first path, lower frequencies for second and third paths) rather than uniform frequencies. This asymmetric approach reduces the impact of path mismatches because the different frequencies create different noise folding patterns that average out, making the system more robust to manufacturing variations and path mismatches.

Inventive Principle:
Principle #4Asymmetry

3Manufacturing precision

If all paths use the same chopping frequency, then path matching is simplified, but noise folding cannot be effectively avoided

Engineering Contradiction:
Improvepath matchingVSAvoidquantization noise folding
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the chopping frequency parameter across different paths rather than keeping it uniform. The first path operates at fs/2 while the second and third paths use lower frequencies, creating a parameter variation that simultaneously avoids quantization noise folding in the critical first path while maintaining robustness to mismatches through the diversity of frequencies.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230370031A1Chopper circuit for multipath chopper amplifier and corresponding method of chopping
Publication Date: 2023.11.16 BV NXP BV
  • US20230370031A1 patent drawing
  • US20230370031A1 patent drawing
  • US20230370031A1 patent drawing

AI summary

A chopper circuit (100) for a multipath chopper amplifier (201) is described. The chopper circuit (100) comprises a first chopper device (110) in a first circuit path (111), wherein the first chopper device (110) is configured to be controlled by a first clock signal (315), which has a first frequency; and a second chopper device (120) in a second circuit path (121), parallel to the first circuit path (111), wherein the second chopper device (120) is configured to be controlled by a second clock signal (325), which has a second frequency, wherein the first frequency is greater than the second frequency. Furthermore, a corresponding method of chopping an input signal (102) is described.