Multipath RF Filter with Phase-Shifted Branches for Lower Clock Rates
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Solution Overview
Problem
Existing RF communication systems face challenges in effectively filtering frequency components at specific frequencies, leading to inadequate out-of-band rejection and increased complexity and cost due to high clock frequencies required for filtering.
Innovation Solution
The implementation of a multipath filter with parallel filter circuit branches, each equipped with a double-in double-switched downconverter, filter networks, and upconverters, using clock signals of the same frequency but different phases to downconvert, filter, and upconvert signals, thereby controlling the center frequency and reducing clock frequency requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-path filters are used to achieve adequate out-of-band rejection, then filtering performance is improved, but device complexity and cost increase
Solution Approach 1:
The filter is divided into multiple parallel circuit branches, each handling a specific frequency component. Each branch contains a downconverter, filter network, and upconverter operating at different clock phases, allowing independent optimization of each path while achieving overall superior out-of-band rejection through parallel operation
Solution Approach 2:
Multiple clock signals with different phases are used to periodically switch the parallel circuit branches. By cycling through different phase combinations, the filter achieves enhanced rejection of out-of-band frequencies while maintaining lower individual clock frequencies, reducing complexity compared to single high-frequency paths
2Reliability
If high clock frequencies are used to achieve adequate filtering performance, then out-of-band rejection is improved, but device complexity and cost increase
Solution Approach 1:
The filtering function is segmented across multiple parallel branches, each operating at a lower clock frequency. By dividing the overall filtering task among several paths with different phase offsets, the system achieves the equivalent of high-frequency filtering using lower, more manageable clock rates in each individual branch
Solution Approach 2:
Multiple lower-frequency clock signals are merged through the parallel circuit architecture to achieve the effective filtering performance of a single high-frequency clock. The combined output of all parallel branches provides the same out-of-band rejection as would require a much higher individual clock frequency
3Reliability
If multiple parallel filter branches are used to improve out-of-band rejection, then filtering performance is improved, but device complexity increases
Solution Approach 1:
Each parallel circuit branch is designed as a universal module capable of handling different frequency components through phase-differentiated clocking. The same basic circuit topology (downconverter-filter-upconverter) is reused across multiple branches with different phase configurations, reducing design complexity despite the increased number of branches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved out-of-band rejection, reduced complexity, and lower costs by using a relatively slow clock signal, while maintaining signal quality and suppressing even order harmonics, thus enhancing the performance of RF filters.
Implementation Method 1
a double-in double-switched downconverter configured to generate a downconverted signal by downconverting the input signal with a pair of clock signals of a common clock signal frequency but of different phases
Implementation Method 2
a filter network configured to filter the downconverted signal to generate a filtered signal
Implementation Method 3
an upconverter configured to upconvert the filtered signal
Data Source
AI summary
Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.