Multipath Memory Mapping Between Coherent and MMIO Domains
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Solution Overview
Problem
Existing processor systems statically assign memories to either a cache coherent domain or an I/O domain, limiting flexibility and preventing users from changing these assignments, which can hinder optimal performance based on changing needs.
Innovation Solution
Implementing a processor system with assignable and non-assignable memories, where assignable memories can be dynamically assigned to either a cache coherent or I/O domain, using a switch to route data based on these assignments, and informing the operating system of these changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memories are statically assigned to cache coherent or I/O domains at implementation time, then the system has clear domain boundaries and simplified design, but the system loses flexibility and cannot be reassigned to different domains
Solution Approach 1:
The patent implements dynamic memory domain assignment where memories can be reassigned between cache coherent and I/O domains at runtime through configuration registers, rather than being fixed at implementation time. This allows the system to adapt to different use cases while maintaining manageable complexity through structured control mechanisms.
Solution Approach 2:
The patent changes the assignment parameter from fixed (static) to variable (dynamic) by introducing configuration registers that control memory domain assignment. This allows the same hardware to operate in different modes based on software configuration, resolving the contradiction between flexibility and complexity.
2Productivity
If memories are statically assigned to either cache coherent or I/O domain, then the hardware interconnect has simpler routing logic, but the system cannot optimize performance for different use cases
Solution Approach 1:
The patent enables the operating system to self-configure memory domain assignments based on actual workload requirements. The OS reads configuration registers and writes appropriate values to assign memories to cache coherent or I/O domains, allowing performance optimization without complex manual configuration procedures.
Solution Approach 2:
The patent prepares memory domain assignment capabilities in advance through configuration registers that can be programmed at any time. This preliminary setup allows the system to quickly switch between different memory domain configurations to optimize performance for different applications without requiring physical reconfiguration.
3Adaptability or versatility
If a switch is added to route data based on memory assignment, then memory domain flexibility is improved, but the device complexity increases
Solution Approach 1:
The patent designs the switch to handle both cache coherent and I/O domain routing through a single unified structure. The switch uses configuration registers to determine routing behavior, allowing one component to serve multiple functions (routing to either domain) based on software control, thereby improving flexibility without proportionally increasing complexity.
Data Source
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AI summary
Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.