Multipath Selection Circuit for Display Panels
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Solution Overview
Problem
Existing multipath selectors in display panels face limitations in performance, particularly in adapting between 1:2 and 1:3 operating modes, which restrict their adaptability and efficiency in handling data signals.
Innovation Solution
A multipath selection circuit is designed with a switch circuit and drive circuit that can operate in both 1:2 and 1:3 modes by using a control signal and timing signal to selectively transmit data signals to switching transistors, allowing for time division control of data lines and timing lines, enabling flexible mode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a multipath selector is designed for a fixed operating mode (1:2 or 1:3), then the circuit structure can be simplified, but the adaptability to different display requirements is reduced
Solution Approach 1:
The patent implements a dynamic multipath selector that can switch between 1:2 and 1:3 operating modes through control signals. The switch circuit includes multiple switching transistors (first switching transistor, second switching transistor, third switching transistor, fourth switching transistor) that can be selectively activated based on the operating mode requirement, enabling the circuit to adapt its configuration dynamically rather than being fixed.
Solution Approach 2:
The patent designs a universal multipath selector that can perform both 1:2 and 1:3 demultiplexing functions using the same physical circuit components. By incorporating multiple switching transistors and control logic, the circuit achieves multi-functionality where the same hardware structure supports different operating modes, eliminating the need for separate dedicated circuits for each mode.
2Adaptability or versatility
If the multipath selector uses multiple data lines for different operating modes, then the adaptability improves, but the signal transmission complexity and potential for unequal load distribution increases
Solution Approach 1:
The patent merges the functionality of multiple data lines into a unified switch circuit architecture. The first data line, second data line, and third data line are all routed through the same switching transistor network, allowing the circuit to select which data line connects to which pixel column based on the operating mode. This merging reduces the complexity of managing separate transmission paths for different modes.
Solution Approach 2:
The switching transistors act as intermediaries between the multiple data lines and the pixel columns. The control signals modulate these intermediary switching elements to route data appropriately, preventing direct complex interconnections between data lines and pixels while maintaining flexible adaptability through the mediating switch network.
3Reliability
If the multipath selector is designed to handle unequal loads in different pixel columns, then the image quality improves, but the circuit complexity and manufacturing difficulty increases
Solution Approach 1:
The patent implements local quality control by assigning different switching transistor configurations to different pixel columns. The first pixel column, second pixel column, third pixel column, and fourth pixel column each have dedicated switching paths that can be independently controlled. This allows unequal load distribution to be managed locally at each column rather than requiring complex global balancing, simplifying manufacturing while maintaining image quality.
Data Source
AI summary
A multipath selection circuit includes a first data line, a second data line, a third data line, a control line, a timing line, a switch circuit, and a drive circuit. The drive circuit includes a first switching transistor and a second switching transistor. The switch circuit is configured to receive a control signal, timing signal, first data signal, second data signal and third data signal, and operate in a first operating mode or a second operating mode according to the control signal and the timing signal. In the first operating mode, the switch circuit is configured to transmit the second data signal to the first switching transistor and the second switching transistor in a time division manner; and in the second operating mode, the switch circuit is configured to transmit the first data signal to the first switching transistor and the third data signal to the second switching transistor.