Multipatterning Gate Processing for Nanosheet SRAM Threshold Balance
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Solution Overview
Problem
Existing SRAM cells in semiconductor integrated circuits face challenges in achieving balanced threshold voltage and critical dimension uniformity, particularly in multi-gate devices like FinFETs and GAA transistors, due to issues with work function material removal processes that can damage high-k and fin structures.
Innovation Solution
A high power, high flow rate dry etch process is employed to selectively remove work function material from NFET structures while preserving it on adjacent PFET structures, using a multi-patterning gate processing technique to enhance critical dimension uniformity and avoid damage to high-k and fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove work function material, then material removal is achieved, but damage occurs to high-k and fin structures
Solution Approach 1:
The patent modifies etching process parameters including using chlorine-based chemistry with specific gas flow rates and power levels to achieve selective removal of work function material while preserving high-k dielectric and fin structures. The etch selectivity is controlled by adjusting process parameters such as pressure, temperature, and gas composition.
Solution Approach 2:
The patent introduces a sacrificial coating layer as an intermediary between the etch process and the underlying structures. This coating protects sensitive high-k and fin structures during etching while allowing controlled removal of work function material, thereby mediating the harmful interaction between the etch plasma and vulnerable structures.
2Manufacturing precision
If multi-patterning gate processing is implemented, then critical dimension uniformity is improved, but process complexity increases
Solution Approach 1:
The patent divides the gate patterning process into multiple discrete steps including initial patterning, spacer formation, and selective etching stages. Each step creates a portion of the final multi-patterned structure, allowing precise control over critical dimensions while managing overall process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
The patent performs preliminary actions such as forming sacrificial spacers and protective coatings before the final etching step. These preliminary structures guide the subsequent selective removal processes and ensure uniform critical dimensions are achieved before the actual work function material removal takes place.
3Reliability
If work function material is removed from NFET structures, then threshold voltage balance is improved, but work function layer integrity is compromised
Solution Approach 1:
The patent applies selective etching that targets only specific regions where work function material needs removal (NFET structures) while leaving work function layers intact in other regions (PFET structures). This localised approach achieves threshold voltage balance in NFETs without compromising the work function layer integrity needed for proper PFET operation.
Solution Approach 2:
The patent employs controlled partial removal of work function material through selective etching processes. Rather than complete removal, the process removes only the necessary portion to achieve target threshold voltage specifications while maintaining sufficient work function layer thickness to preserve electrical integrity and prevent damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves threshold voltage balance and critical dimension uniformity in SRAM devices by maintaining the integrity of work function layers, leading to better performance and reduced damage during processing.
Implementation Method 1
A high power, high flow rate dry etch process is employed to selectively remove work function material from NFET structures
Implementation Method 2
etch process with a chlorine-based chemistry
Data Source
AI summary
Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).