Multi-Patterning Aware Parasitic Extraction for IC Timing Accuracy

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Solution Overview

Problem

Advanced process node manufacturing in integrated circuit (IC) fabrication faces challenges due to multi-patterning lithography, which introduces timing variations and errors in parasitic extraction, particularly due to mask misalignment affecting coupling capacitances, requiring a multi-patterning aware modeling solution for accurate signoff and performance.

Innovation Solution

A method for parasitic extraction in IC design that determines resistance and capacitance solutions, captures multi-patterning sources of variation, and calculates sensitivities to generate statistical parasitics in vector or collapsed reduced vector form, accounting for geometrical shifts and variations across different layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multi-patterning lithography is used to achieve advanced process node manufacturing, then manufacturing precision is improved, but timing variations and parasitic extraction errors increase due to mask misalignment

Engineering Contradiction:
Improveprintability of device and interconnect layersVSAvoidaccuracy of parasitic extraction
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent changes the parameter approach by introducing multi-patterning awareness into the parasitic extraction process. It captures sources of variation related to mask misalignment and uses sensitivity analysis to adjust parasitic values, transforming the extraction from a static geometric calculation to a dynamic model that accounts for manufacturing variations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by capturing sources of variation from multi-patterning processes and using sensitivity calculations to adjust parasitic values. The system continuously refines parasitic extraction results by incorporating feedback about mask misalignment and geometric variations, leading to more accurate timing analysis.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If multi-patterning lithography is used to ensure printability, then device and interconnect layer fabrication is improved, but coupling capacitance variations increase due to mask misalignment

Engineering Contradiction:
ImproveprintabilityVSAvoidtiming analysis accuracy
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by capturing sources of variation specific to different regions and patterns in the multi-patterning process. It performs sensitivity analysis for different geometric configurations and mask misalignment scenarios, allowing timing analysis to account for local variations in coupling capacitances rather than using uniform assumptions.

Inventive Principle:
Principle #3Local quality

3Device complexity

If traditional parasitic extraction is used without multi-patterning awareness, then extraction process is simpler, but timing analysis and signal integrity analysis become inaccurate

Engineering Contradiction:
Improveparasitic extraction processVSAvoidsignoff accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary action by capturing sources of variation and calculating sensitivities before final parasitic extraction. It pre-computes sensitivity factors that account for multi-patterning effects, which are then applied during the extraction process to adjust parasitic values, ensuring accuracy without requiring complete redesign of the extraction architecture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8769452B2Parasitic extraction in an integrated circuit with multi-patterning requirements
Publication Date: 2014.07.01 GLOBALFOUNDRIES US INC
  • US8769452B2 patent drawing
  • US8769452B2 patent drawing
  • US8769452B2 patent drawing

AI summary

Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.