Multiphase CDAC Unit Cell for mmWave RF DAC Linearity
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Solution Overview
Problem
Existing RF Digital-to-Analog Converters (DACs) face challenges in operating effectively at mmWave frequencies, particularly with polar converters becoming difficult or impossible to employ, which affects the performance of 5G and new radio (NR) systems that require higher bandwidths.
Innovation Solution
The use of multiphase Capacitive DACs (CDACs) with tunable matching networks that provide small variability in gain attenuation, good linearity, and constant input and output impedance, enabling efficient operation at mmWave frequencies by employing a differential structure and mirroring techniques to manage phase changes and reduce power drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polar converters are employed in RF DACs, then good linearity and performance are achieved at lower frequencies, but they become difficult or impossible to employ at mmWave frequencies
Solution Approach 1:
The patent transitions from polar converter architecture to multiphase CDAC architecture, fundamentally changing the operating parameters and frequency characteristics of the RF DAC. This parameter change enables operation at mmWave frequencies while maintaining good linearity through the use of multiple phased capacitive DACs with specific phase relationships.
Solution Approach 2:
The patent divides the RF DAC into multiple separate CDAC units, each handling a specific phase component. This segmentation allows each unit to operate independently at high frequencies, avoiding the bandwidth limitations of monolithic polar converters while maintaining overall system linearity through coherent combination of phased outputs.
2Quantity of substance
If mmWave frequency bands are employed to increase bandwidth, then available bandwidth is significantly increased, but existing techniques and components are not well adapted to operating at these higher frequencies
Solution Approach 1:
The patent changes the fundamental operating parameters of the RF DAC by adopting multiphase CDAC architecture with specific phase relationships and capacitor switching schemes that are optimized for mmWave operation, enabling the system to effectively utilize high-frequency bandwidth while maintaining signal integrity.
Solution Approach 2:
The patent employs dynamic phase switching and capacitor activation schemes that adapt the RF DAC operation to different frequency conditions, allowing seamless operation across a wide frequency range including mmWave bands by dynamically adjusting which capacitive elements are active based on the required phase and frequency.
3Power
If multiphase CDAC with mirroring techniques is employed, then power drop is reduced and linearity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple CDAC units with complementary phase relationships and uses mirroring techniques to combine their outputs, achieving power enhancement and improved linearity through constructive interference while managing complexity through systematic integration of the merged signal paths.
Solution Approach 2:
The patent designs the multiphase CDAC system to perform multiple functions simultaneously: individual CDAC units handle different phase components, the mirroring technique provides both power enhancement and linearity improvement, and the overall architecture maintains adaptability across frequency ranges, reducing the need for separate optimization circuits.
Data Source
AI summary
CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.