Multi-Phase Clock A/D Conversion for High-Resolution Imaging
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Solution Overview
Problem
Existing imaging elements face challenges in achieving high speed and high resolution A/D conversion due to the difficulty in increasing the frequency of the reference clock, which needs to be distributed to all columns, making it hard to operate efficiently.
Innovation Solution
The use of a phase-difference clock generation unit with multiple phase interpolators to generate multi-phase clock signals, which are then used for A/D conversion, allowing for higher resolution and speed without the need for increased clock frequency across all columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the reference clock is increased to achieve high speed or high resolution, then the A/D conversion speed and resolution are improved, but the difficulty of distributing the reference clock to all columns increases
Solution Approach 1:
The patent divides the single high-frequency reference clock into multiple lower-frequency clock signals distributed to different column groups. Each column group has its own A/D converter operating at lower frequency, which processes pixel signals and outputs digital data. This segmentation resolves the contradiction by maintaining high overall conversion capability while reducing the burden on individual clock distribution paths.
Solution Approach 2:
The patent introduces a two-dimensional clock distribution architecture: horizontally dividing columns into multiple groups with separate A/D converters, and vertically using a time-division multiplexed reference clock distribution. This dimensional approach allows high-resolution conversion without requiring all columns to simultaneously handle high-frequency clocks, thus resolving the distribution complexity issue.
2Measurement precision
If the frequency of the reference clock is increased to achieve high resolution, then the conversion resolution is improved, but the power consumption increases
Solution Approach 1:
The patent segments the A/D conversion function across multiple column groups, each with its own converter operating at lower frequency. This segmentation allows the system to achieve high overall resolution through parallel processing of multiple lower-frequency conversions, rather than requiring a single high-frequency conversion, thereby reducing power consumption while maintaining resolution.
Solution Approach 2:
The patent implements time-division multiplexing where the reference clock is distributed to different column groups at different time periods. Each column group receives the reference clock intermittently rather than continuously at high frequency, achieving the required conversion resolution through accumulated partial actions over time, which significantly reduces power consumption compared to continuous high-frequency operation.
3Productivity
If the frequency of the reference clock is increased to achieve high speed, then the conversion speed is improved, but the circuit size increases
Solution Approach 1:
The patent segments the conversion function across multiple column groups with distributed A/D converters. Each converter operates at lower frequency with simpler circuitry, reducing the size of individual conversion circuits. The overall high-speed capability is achieved through parallel processing across multiple segments, resolving the contradiction between speed and circuit size.
Solution Approach 2:
The patent employs a two-dimensional architecture where conversion capacity is distributed across multiple column groups (horizontal dimension) and time-division multiplexed (vertical dimension). This dimensional distribution allows the system to achieve high overall conversion speed without requiring large high-frequency conversion circuits in each column, thus reducing total circuit size while maintaining speed performance.
Data Source
AI summary
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.