Multi-Phase Clock Generator with Adaptive Delay Locking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional multi-phase clock signal generators face difficulties in initializing clock signals with varying frequencies and duty cycle distortions, leading to improper phase relationships and synchronization issues, especially as clock frequencies increase and timing requirements become more stringent.

Innovation Solution

The proposed solution involves a multi-phase clock signal generator with a delay line having multiple delay elements per tap, a phase detector that synchronizes C0, C180, and C360 signals in a single adjustment, and a reset pulse generator to minimize adjustment time and prevent over-shoot, allowing for adaptive delay control and improved locking speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a conventional multi-phase clock signal generator is used with a single delay element per tap, then the device complexity is reduced, but the initialization time increases and locking speed decreases

Engineering Contradiction:
Improveinitialization timeVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The delay line is segmented into multiple delay elements (first, second, third delay elements) connected in series between each tap point. This segmentation allows for finer control of phase relationships and faster initialization by enabling independent adjustment of multiple delay stages, resolving the contradiction between reduced complexity and faster locking speed.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If a fixed timing circuit is used to generate quadrature signals, then the device complexity is reduced, but the adaptability to varying clock frequencies is lost

Engineering Contradiction:
Improveadaptability to clock frequenciesVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The circuit employs adjustable delay elements with control inputs that allow the delay characteristics to be dynamically modified based on the input clock frequency. This dynamic adjustment capability enables the circuit to adapt to a wide range of clock frequencies while maintaining proper phase relationships, resolving the contradiction between adaptability and device complexity.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If the number of delay elements per tap is increased, then the measurement precision of phase relationships is improved, but the device complexity increases

Engineering Contradiction:
Improvephase relationship precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple delay elements are concentrated at critical tap points (such as C0, C180, C360) rather than uniformly distributed throughout the delay line. This local quality approach provides enhanced phase relationship precision at key synchronization points while limiting the overall increase in device complexity by focusing the additional components where they are most needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8704560B2Multi-phase signal generator and method
Publication Date: 2014.04.22 MICRON TECHNOLOGY INC
  • US8704560B2 patent drawing
  • US8704560B2 patent drawing
  • US8704560B2 patent drawing

AI summary

A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.