Multi-Phase Clock Divider Latch Architecture for High-Frequency Accuracy
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Solution Overview
Problem
Existing multi-phase clock divider circuits fail to accurately divide high-frequency clock signals while maintaining the phase relationship, leading to insufficient high-data latch time, which affects the accuracy of frequency division.
Innovation Solution
A divider circuit configuration that includes a main latch circuit and a sub-latch circuit, where the main latch circuit receives reference clock signals to initiate frequency division and outputs inverted data signals, which are then used by the sub-latch circuit to generate frequency-divided clock signals, ensuring sufficient data latch time and maintaining phase relationship across all latch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased or the number of phases is increased, then the productivity and adaptability of the booster circuit are improved, but the high-data latch time becomes insufficient and the accuracy of frequency division deteriorates
Solution Approach 1:
The divider circuit is divided into multiple latch circuits (DFF0-DFF7) that process different phases of the clock signal independently. Each latch circuit handles a specific phase, allowing the circuit to maintain accuracy at high frequencies by distributing the frequency division task across multiple specialized units rather than using a single sequential circuit.
Solution Approach 2:
The circuit transitions from sequential time-based processing to parallel spatial processing by utilizing multiple latch circuits operating simultaneously on different phases. This dimensional shift from time-sequential to space-parallel architecture enables the circuit to maintain sufficient latch time for each phase while processing high-frequency multi-phase clock signals.
2Productivity
If the high-frequency multi-phase clock signal is used, then the productivity of the booster circuit is improved, but the phase relationship maintenance becomes difficult and reliability deteriorates
Solution Approach 1:
The circuit uses the output of each latch circuit as feedback input to the next latch circuit in the sequence. This feedback mechanism ensures that phase relationships are maintained across all latch circuits, as each stage is synchronized with the previous stage through the clock signal phases, providing reliable phase coordination at high frequencies.
Solution Approach 2:
The circuit exploits the phase parameter of the clock signal by designing latch circuits that are triggered by specific phases (CLK0-CLK7). By changing the triggering parameter from a single clock edge to multiple phase-specific clock edges, the circuit maintains reliable phase relationships while operating at high frequencies suitable for boost operations.
Data Source
AI summary
A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.