Multi-Phase Clock Generation With Dual Locking for Phase Accuracy
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Solution Overview
Problem
Conventional semiconductor devices face challenges in maintaining accurate phase differences between multi-phase clocks due to duty ratio changes, leading to phase errors that impair clock credibility as frequency increases.
Innovation Solution
An apparatus and method for generating multi-phase clocks that secure a desired delay time using a clock delay, clock multiplexer, phase detector, and control voltage signal generator, performing dual locking operations to ensure precise phase differences even with duty ratio changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single locking operation is used to generate multi-phase clocks, then device complexity is reduced, but phase precision deteriorates due to duty ratio changes causing phase errors
Solution Approach 1:
The locking operation is segmented into two distinct phases: first locking operation that locks a delayed clock to a source clock, and second locking operation that locks a further delayed clock to the source clock. This segmentation allows each locking operation to independently establish precise phase relationships, thereby achieving high phase precision without requiring an overly complex single locking mechanism
Solution Approach 2:
A phase detector serves as an intermediary component that monitors phase differences between clocks and generates control signals to adjust delay times. This intermediary mechanism enables automatic compensation for duty ratio changes, maintaining phase precision without manually increasing system complexity
2Speed
If clock frequency is increased to improve operation speed, then productivity increases, but phase stability deteriorates due to amplified phase errors from duty ratio changes
Solution Approach 1:
The system implements feedback mechanisms where phase detectors continuously monitor phase differences and generate control signals that adjust delay times in real-time. This feedback loop compensates for duty ratio changes and maintains phase stability even at high operating frequencies, allowing productivity improvement without sacrificing reliability
Solution Approach 2:
The delay times of clock delay circuits are made dynamically adjustable through control signals generated by phase detectors. This dynamic adjustment capability allows the system to adapt to duty ratio changes and maintain phase stability across varying operating conditions and frequencies
3Adaptability or versatility
If duty ratio is changed to adapt to different operating conditions, then adaptability improves, but phase accuracy deteriorates due to phase differences between multi-phase clocks
Solution Approach 1:
The system changes the delay time parameter of clock delay circuits based on feedback from phase detectors. When duty ratio changes occur, the phase detectors detect resulting phase errors and generate control signals that adjust delay times to compensate, thereby maintaining phase accuracy while preserving duty ratio adaptability
Data Source
AI summary
An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.