Multi-Phase Clock Generator With Delay-Line Duty Error Correction
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Solution Overview
Problem
Existing multi-phase clock generators for memory devices are complex and power-intensive, occupying large areas due to the use of complicated multi-phase detectors, which complicates the synchronization of data with clock signals in high-speed DRAM systems.
Innovation Solution
A multi-phase clock generator with a simplified structure that includes a first and second variable delay line, a fixed delay line, a delay line controller, a phase controller, phase splitters, and duty cycle detectors to correct duty errors and phase differences using a delay locked loop, reducing power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complicated multi-phase detector is used in the clock generator, then phase detection capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the clock generation system into multiple independent variable delay lines (first, second, third variable delay lines) each handling specific phase adjustments. This segmentation allows simpler individual components to work together to achieve complex multi-phase clock generation without requiring a complicated multi-phase detector
Solution Approach 2:
The patent introduces delay lines as intermediary components between the reference clock and the output clocks. These delay lines act as mediators that adjust phase differences through controlled delay, eliminating the need for complex phase detection and correction circuits
2Measurement precision
If a complicated multi-phase detector is used in the clock generator, then phase detection capability is improved, but power consumption increases
Solution Approach 1:
The patent replaces the mechanical/electronic multi-phase detector system with a delay-based phase adjustment system. By using variable delay lines controlled by control signals, the system achieves phase synchronization through time-delay manipulation rather than complex detection and correction, significantly reducing power consumption
3Manufacturing precision
If more delay lines and control circuits are added to correct phase skew, then phase synchronization accuracy is improved, but device area increases
Solution Approach 1:
The patent designs variable delay lines that can serve multiple functions: they provide both the primary delay function and the phase adjustment function simultaneously. The same delay line structure is reused across different clock paths (first, second, third variable delay lines), allowing multi-phase clock generation with reduced area compared to having separate circuits for each function
Data Source
AI summary
A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.