Multi-Phase Clock Generator for Skew-Tolerant Duty Cycle Control
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Solution Overview
Problem
High-speed data transmission in multi-phase signaling systems faces challenges due to skew between bits, leading to duty cycle distortion and jitter in clock signals, which results in bit errors.
Innovation Solution
A non-overlapping clock generator circuit that processes bit signals from a multi-phase receiver, using pull-down and pull-up signals to manage skew between bits, ensuring a constant clock duty cycle by discharging and recharging a common node with controlled delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional multi-wire bus transmission is used, then data transmission can occur over multiple independent wires, but skew between bits increases as data rates increase
Solution Approach 1:
The patent merges multiple independent bit transmission lines into a single serialized transmission line, where multiple bits are transmitted sequentially over one wire rather than simultaneously over multiple wires. This eliminates the skew problem between bits on different wires while maintaining high data transmission rates through serialization.
Solution Approach 2:
The patent employs periodic clock signaling to synchronize the serialized bit transmission, using regular clock cycles to transmit each bit in sequence. This periodic action ensures that bits are transmitted at consistent intervals, eliminating skew while maintaining high data rates through the regular rhythm of serialization and deserialization.
2Manufacturing precision
If SERDES systems are used to eliminate bit skew, then a single transmission line is used for serialized transmission, but inter-symbol interference occurs at data rates exceeding 10 GHz
Solution Approach 1:
The patent combines multiple SERDES channels into a multi-phase signaling system where three separate transmission lines are used in coordination. By merging the capabilities of multiple channels and using them simultaneously with proper phase relationships, the system achieves data rates exceeding 10 GHz without the inter-symbol interference that limits single-channel SERDES systems.
Solution Approach 2:
The patent transitions from single-dimensional serialized transmission to multi-dimensional parallel transmission by utilizing three separate transmission lines with different phases. This dimensional expansion allows the system to overcome the bandwidth limitations of single-channel SERDES while maintaining signal integrity through the spatial separation provided by multiple transmission lines.
3Speed
If three-phase signaling is used to increase data transmission rates, then data rates can be more than doubled over binary transmission, but duty cycle distortion and jitter occur in clock generation
Solution Approach 1:
The patent introduces a dedicated clock recovery circuit as an intermediary component that extracts and regenerates the clock signal from the multi-phase transmitted data. This intermediary clock circuit eliminates duty cycle distortion and jitter by regenerating clean clock signals from the received data, separating the clock function from the data transmission paths and ensuring precise timing for high-speed operation.
Solution Approach 2:
The patent employs feedback mechanisms in the clock recovery circuit where the received signal is used to regenerate and synchronize the clock signal. By continuously adjusting the clock phase and duty cycle based on feedback from the actual transmitted and received data, the system maintains precise timing even at high data rates exceeding 10 GHz, eliminating the duty cycle distortion that would otherwise occur.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A~2C
AI summary
A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.