Multi-Phase Clock Randomization for TI ADC Phase Error Whitening
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for eliminating clock phase errors in time-interleaved analog-to-digital converters (TI ADCs) face challenges such as high complexity, limited stability, and inability to real-time track and correct phase errors that vary with the working environment, leading to performance deterioration.
Innovation Solution
A circuit for generating a multi-phase clock with random disturbance, comprising a main clock module, a random signal generation module, and a buffer matrix switch module, which pre-trims and randomly switches the clock signals to transform fixed phase errors into irregular clock jitter, effectively whitening the phase error and reducing its impact on spurious components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If foreground trimming method is used to eliminate clock phase error, then implementation simplicity and stability are improved, but ability to track and correct phase error fluctuations with environmental changes deteriorates
Solution Approach 1:
The patent applies preliminary action by performing foreground trimming to establish an initial phase correction baseline before operation. This preliminary correction handles the majority of phase errors under nominal conditions, while the background correction mechanism continuously adjusts for environmental variations. The delay line module is pre-configured with multiple tap points to provide preliminary phase adjustment capabilities.
Solution Approach 2:
The patent implements feedback through background real-time correction that continuously monitors clock phase errors and dynamically adjusts correction parameters. The system uses feedback from phase error detection to update correction values, enabling continuous tracking of phase fluctuations caused by environmental changes while maintaining the simplicity of foreground trimming.
2Adaptability or versatility
If background real-time correction method is used to eliminate clock phase error, then ability to track and correct phase error fluctuations is improved, but circuit design complexity increases
Solution Approach 1:
The patent segments the clock correction function into two independent modules: foreground trimming for initial correction and background real-time correction for continuous adjustment. This segmentation allows each module to be optimized independently, reducing overall complexity. The delay line module is segmented into multiple tap points, each providing discrete phase correction options without requiring complex continuous adjustment mechanisms.
Solution Approach 2:
The patent introduces an intermediary delay line module with multiple tap points that mediates between the main clock signal and the corrected clock output. This intermediary structure provides a simple yet effective means of phase adjustment without requiring complex correction circuits, bridging the gap between foreground trimming and background correction functions.
3Stability of the object's composition
If conventional foreground trimming is used, then stability is improved, but real-time correction capability deteriorates
Solution Approach 1:
The system performs preliminary foreground trimming to establish a stable baseline correction that remains fixed during operation, providing system stability. This preliminary action handles the dominant phase errors under nominal conditions, ensuring stable operation while enabling supplementary real-time correction for environmental variations.
Solution Approach 2:
The system implements feedback through background correction that continuously monitors phase errors and dynamically adjusts correction parameters in real-time. This feedback mechanism enhances reliability by automatically tracking and correcting phase fluctuations caused by environmental changes, while the stable foreground trimming provides a reliable baseline.
Data Source
AI summary
The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.