Clock Generating Circuit Without a Phase Rotator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock data recovery circuits are costly due to the large area occupied and complex operation of phase rotators, which are necessary for generating and synchronizing clock signals with digital data.
Innovation Solution
A clock data recovery circuit utilizing a phase selector to choose an output clock as a feedback clock from a plurality of output clocks, comprising a phase detector, controllable oscillator, phase selector, and phase difference comparator, which generates and synchronizes output clocks with a data signal without the need for a phase rotator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase rotator is used to generate and synchronize clock signals with digital data, then the clock signal synchronization is achieved, but the circuit area and complexity increase significantly
Solution Approach 1:
The patent extracts and removes the phase rotator component from the clock data recovery circuit. Instead of using a complex phase rotator to adjust phases of multiple clock signals, the invention directly selects one clock signal from multiple phase-shifted clocks generated by the controllable oscillator, thereby eliminating the need for phase rotation operations and reducing circuit complexity while maintaining synchronization capability
Solution Approach 2:
The controllable oscillator is designed to generate multiple clock signals with different phases internally, making the oscillator itself perform the function that would otherwise require a separate phase rotator. This multi-functional approach consolidates the phase adjustment capability into the oscillator, reducing the overall number of components and circuit complexity
2Reliability
If a phase rotator is used to generate and synchronize clock signals with digital data, then the clock signal synchronization is achieved, but the circuit area occupied increases
Solution Approach 1:
The patent extracts and removes the phase rotator component from the clock data recovery circuit. Instead of using a complex phase rotator to adjust phases of multiple clock signals, the invention directly selects one clock signal from multiple phase-shifted clocks generated by the controllable oscillator, thereby eliminating the need for phase rotation operations and reducing circuit complexity while maintaining synchronization capability
Solution Approach 2:
The patent merges the phase adjustment function into the controllable oscillator by having it generate multiple phase-shifted clock signals internally. This consolidation eliminates the need for a separate phase rotator block, thereby reducing the total circuit area occupied while maintaining the ability to synchronize clock signals with digital data
3Reliability
If conventional clock data recovery circuit is used, then the clock signal can be recovered and synchronized, but the cost of the transceiver increases
Solution Approach 1:
The patent extracts and removes the phase rotator component from the clock data recovery circuit. Instead of using a complex phase rotator to adjust phases of multiple clock signals, the invention directly selects one clock signal from multiple phase-shifted clocks generated by the controllable oscillator, thereby eliminating the need for phase rotation operations and reducing circuit complexity while maintaining synchronization capability
Solution Approach 2:
The patent replaces the expensive phase rotator with a simpler and more cost-effective phase selector that directly chooses one clock signal from multiple phase-shifted clocks. This substitution uses less complex, more manufacturable components while achieving the same functional outcome of clock signal synchronization, thereby reducing the overall manufacturing cost of the transceiver
Data Source
AI summary
A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a controllable oscillator for generating a plurality of output clocks according to the control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; a feedback circuit for generating the input clock according to the feedback clock; and a phase difference comparator for comparing the plurality of phases corresponding to the plurality of output clocks respectively with a data phase of a data signal to generate a compared result, and generating the phase select signal according to the compared result.


