Multi-Phase Clock Generation With Fewer Delay Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices that generate multi-phase clock signals require a large number of delay elements, leading to increased circuit scale, which is inefficient for handling growing data volumes and high processing speeds.
Innovation Solution
A semiconductor device with cascade-connected delay circuits and a control circuit that adjusts delay amounts to produce multi-phase clock signals with different phases, along with a data processing circuit that converts data signals between parallel and serial formats, reducing the need for numerous delay elements and minimizing circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large number of delay elements are used to generate multi-phase clock signals, then the phase interval can be shortened, but the circuit scale increases greatly
Solution Approach 1:
The patent divides the delay generation function into multiple segments by using a single delay element in conjunction with a multi-phase clock signal distribution system. Instead of using one large number of delay elements, the system segments the clock signal into multiple phases and distributes them to different data processing circuits, achieving the effect of multiple delay stages with a single physical delay element.
Solution Approach 2:
The single delay element serves multiple functions by generating multiple phased clock signals that are distributed to various data processing circuits. This multi-functional approach allows one delay element to replace what would traditionally require many delay elements, reducing circuit scale while maintaining processing capability.
2Ease of manufacture
If the circuit scale is reduced by using fewer delay elements, then manufacturing efficiency improves, but generating multi-phase clock signals becomes more difficult
Solution Approach 1:
The patent introduces a clock signal distribution system as an intermediary between the single delay element and the multiple data processing circuits. This intermediary distributes the delayed clock signal into multiple phases, simplifying the overall system while maintaining the capability to generate multi-phase clock signals. The distribution system acts as a mediator that resolves the conflict between reduced component count and clock signal generation requirements.
3Productivity
If more delay elements are used to achieve shorter phase intervals, then data processing speed increases, but the number of components and circuit complexity increase
Solution Approach 1:
The patent implements dynamic clock signal distribution where a single delay element dynamically generates multiple phased clock signals that are distributed to different data processing circuits. This dynamic approach allows the system to achieve high data processing throughput by coordinating multiple circuits with phased clocks, while using far fewer physical delay elements than traditional static approaches would require.
Data Source
AI summary
Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.