Multiphase Clock Generation Using Hybrid Active-Passive Cascades
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Solution Overview
Problem
Conventional multiphase clock generation methods suffer from high power consumption and phase inaccuracy, with exclusively passive approaches degrading phase accuracy and exclusively active approaches consuming more power and exhibiting random variations.
Innovation Solution
A hybrid approach using a cascade of both active and passive clock generation circuits, where active and passive circuits are alternately coupled in series to generate phase-shifted clock signals, reducing power consumption and improving phase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If exclusively passive RC polyphase filters are used for multiphase clock generation, then power consumption is reduced, but phase accuracy is degraded
Solution Approach 1:
The patent combines passive RC polyphase filter circuits with active buffer circuits in a hybrid configuration. The passive filters generate the phase-shifted clock signals while the active buffers amplify and drive the signals without significantly impacting the phase accuracy, thus achieving both low power consumption and high phase accuracy simultaneously.
Solution Approach 2:
The patent introduces buffered stages as intermediary elements between the passive RC filter stages. These buffers act as mediators that isolate the passive filter sections from each other, preventing loading effects that would degrade phase accuracy, while the passive filters continue to operate at low power consumption.
2Measurement precision
If exclusively active circuits are used for multiphase clock generation, then phase accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent merges the advantages of both passive and active circuits by using passive RC filters for phase shifting (low power) and active buffers only where needed for signal driving (maintaining phase accuracy). This hybrid approach eliminates the need for exclusively active circuits while preserving phase accuracy.
Solution Approach 2:
The patent applies active buffering only locally at specific stages where signal driving capability is needed, rather than using active circuits throughout the entire multiphase clock generation chain. This localized application of active circuits minimizes power consumption while maintaining phase accuracy where it matters most.
3Measurement precision
If exclusively active circuits are used for multiphase clock generation, then phase accuracy is maintained, but random variation increases
Solution Approach 1:
The patent combines passive RC filters with active buffers to create a hybrid system that leverages the stability and low noise characteristics of passive circuits for phase generation, while using active buffers only for signal amplification. This reduces the overall random variation compared to exclusively active circuits.
Solution Approach 2:
The patent limits the use of active circuits to specific localized stages, reducing their cumulative random variation effects. The majority of the phase generation is performed by passive circuits which exhibit lower random variation, thereby improving overall reliability while maintaining necessary phase accuracy.
Data Source
AI summary
An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.