Multiphase Clock Recovery Calibration for Jitter and Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current clock generation circuits in multi-wire, multi-phase data communication links, such as the C-PHY interface, face limitations in speed and reliability due to variations in signal transition times, leading to jitter and reduced channel bandwidth, especially as signaling frequencies increase.
Innovation Solution
A method and apparatus for calibrating a clock recovery circuit by incrementally adjusting a delay period until the clock signal matches the desired frequency, ensuring reliable data transmission on a 3-wire, 3-phase interface by suppressing multiple transitions and maintaining the loop delay within the symbol interval, thereby minimizing jitter and maximizing data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay circuits are used to ensure stable signaling states before sampling, then reliability of data transmission is improved, but transmission rate is limited
Solution Approach 1:
The patent implements dynamic delay adjustment by incorporating a delay calibration circuit that automatically adjusts the delay period based on detected transitions. The delay period is no longer fixed but is dynamically optimized during operation, allowing the system to maintain reliability while achieving higher transmission rates by reducing excessive delay.
Solution Approach 2:
The patent changes the delay period parameter from a fixed value to a variable that can be adjusted during calibration. The delay calibration circuit modifies the delay period based on detected transitions, allowing the system to optimize the delay parameter for different operating conditions and achieve higher transmission rates without sacrificing reliability.
2Stability of the object's composition
If maximum delay values are used to accommodate signal variations, then clock signal stability is improved, but channel bandwidth is reduced
Solution Approach 1:
The delay period is made dynamic through calibration, allowing the system to use the minimum necessary delay rather than a fixed maximum value. This dynamic adjustment maintains clock signal stability by adapting to actual signal conditions while preserving channel bandwidth by avoiding excessive delay.
Solution Approach 2:
The delay calibration circuit performs self-adjustment by detecting transitions and automatically setting an appropriate delay period. This self-service mechanism eliminates the need for manual optimization and allows the system to automatically find the optimal delay that maintains stability without unnecessarily reducing bandwidth.
3Reliability
If delay period is increased to suppress multiple transitions, then jitter is reduced, but transmission speed is decreased
Solution Approach 1:
The delay period is dynamically adjusted during calibration to the minimum value needed to suppress multiple transitions. Rather than using a fixed large delay, the system calibrates the delay to exactly what is necessary for jitter reduction, thereby maintaining transmission speed while achieving the required jitter suppression.
Solution Approach 2:
The patent applies partial action by using only the necessary amount of delay to suppress multiple transitions, rather than applying excessive delay. The calibration circuit determines the precise delay needed and applies only that amount, avoiding the performance penalty of over-delaying while still achieving jitter reduction.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.