Multi-Phase Clock Generation With Feedback for Low Jitter Sampling
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Solution Overview
Problem
The increasing demand for high-capacity and high-speed I/Os in wireline transceivers necessitates improved multi-phase sampling techniques, requiring stricter jitter and phase accuracy in multi-phase clocks and phase interpolators, which existing circuits and methods fail to adequately address.
Innovation Solution
The development of circuits comprising a delay line and a ring oscillator with differential unit delay cells and current injection inputs, along with phase interpolators that utilize a two-step multi-phase clock generation scheme to enhance spectral purity and reduce phase noise, breaking the tradeoff between jitter and phase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher data rates are implemented, then I/O capacity and speed are improved, but jitter and phase accuracy requirements become more stringent
Solution Approach 1:
The clock generation system is segmented into multiple independent delay lines (e.g., four delay lines generating 0°, 90°, 180°, 270° phases) rather than using a single multi-phase generator. Each delay line independently generates clock phases, allowing individual optimization and reducing cumulative phase errors, thereby maintaining high phase accuracy at higher data rates.
Solution Approach 2:
A phase detection and feedback mechanism is implemented where phase errors are detected and corrected through feedback control. The system monitors phase accuracy and adjusts delay line parameters dynamically to compensate for drift and errors, ensuring stringent phase accuracy requirements are met even at higher data rates.
2Productivity
If multi-phase sampling is adopted, then ADC speed requirements are relaxed, but clock jitter and phase accuracy become more critical
Solution Approach 1:
Multiple delay lines are merged into a unified multi-phase clock generation system where their outputs are combined to form the final multi-phase sampling clock. This merging approach distributes the jitter burden across multiple independent sources and allows for jitter cancellation through proper phasing, reducing overall clock jitter while maintaining relaxed ADC speed requirements.
Solution Approach 2:
The system dynamically changes delay parameters of individual delay lines to optimize phase distribution and minimize jitter. By adjusting delay line lengths and propagation characteristics, the system can adapt to varying operating conditions and maintain low jitter performance across different sampling rates.
3Device complexity
If phase interpolators are used to generate multi-phase clocks, then device complexity is reduced, but linearity and phase accuracy deteriorate
Solution Approach 1:
Instead of using phase interpolators that approximate intermediate phases (which introduce non-linearity), the invention inverts the approach by directly generating multiple precise phases using separate delay lines. Rather than interpolating from two reference phases, the system generates all required phases (0°, 90°, 180°, 270°) directly, eliminating interpolation non-linearity and improving phase accuracy.
Data Source
AI summary
Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.