Multi-Phase Clock Generator for Low-Skew High-Lane EPHY
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Solution Overview
Problem
As data rates increase in Electrical Physical layer (EPHY) technology, oscillation frequency and phase skew issues arise, particularly when configuring multi-path high-frequency clocks to increased lanes, leading to suboptimal performance in multi-phase clock generators.
Innovation Solution
A multi-phase clock generator system comprising a first oscillator circuit with multiple delay circuits and a second oscillator circuit with fewer delay circuits, where the first oscillator circuit receives multi-phase input clock signals and outputs a greater number of clock signals, and the second oscillator circuit adjusts these signals to ensure uniform phase differences, generating multi-phase output clock signals with the same frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data rate is increased, then the transmission speed is improved, but the oscillation frequency and size of the LCVCO will be increased
Solution Approach 1:
The clock generation process is divided into two separate oscillator circuits: a first oscillator circuit that generates an intermediate clock signal, and a second oscillator circuit that generates the final high-frequency clock signal. This segmentation allows each circuit to operate at optimized frequencies, avoiding the need for a single LCVCO to handle both low and high frequency requirements simultaneously.
Solution Approach 2:
The first oscillator circuit acts as an intermediary between the reference clock and the second oscillator circuit. It generates an intermediate clock signal that is then processed by the second oscillator circuit to produce the final high-frequency clock, serving as a mediator that enables frequency multiplication without requiring the LCVCO to directly generate high-frequency signals.
2Productivity
If multi-path high frequency clocks are configured to increased lanes, then the data transmission capacity is improved, but a phase skew that does not match the design requirements may occur
Solution Approach 1:
The patent employs a feedback mechanism where the first oscillator circuit receives the reference clock and generates an intermediate clock, which is then fed into the second oscillator circuit. This feedback loop allows for precise phase control and synchronization across multiple lanes, ensuring that phase skew remains within design requirements while supporting increased data transmission capacity.
3Device complexity
If the number of delay circuits in the second oscillator circuit is reduced, then the device complexity is reduced, but the ability to generate precise multi-phase signals may be compromised
Solution Approach 1:
The delay circuit functionality is segmented between two oscillator circuits. The first oscillator circuit handles initial phase generation with its delay circuits, while the second oscillator circuit uses fewer delay circuits to refine and distribute the phases. This segmentation allows the second oscillator circuit to have reduced complexity while maintaining precision through the combined effort of both circuits.
Data Source
AI summary
A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.