Multi-Phase Clock Recovery for Multi-Channel Data Rate Variation
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Solution Overview
Problem
In non-clock-forwarded communications systems, implementing multiple clock-and-data-recovery (CDR) circuits for different data streams with varying data rates requires significant layout area and operating power, making it inefficient for integrated circuit applications.
Innovation Solution
A clock-and-data recovery system that includes a multi-phase clock generator producing phase-offset clock signals, which are used by channel circuits to generate output data streams and recovered clock signals, with a logic circuit selecting the appropriate sampling clock signal from these phase-offset signals to sample the input data stream effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CDR circuits are implemented for different data streams, then each data stream can be recovered independently, but layout area and operating power increase significantly
Solution Approach 1:
The patent merges multiple CDR circuits into a single shared CDR circuit that processes multiple data streams sequentially. The sampling clock generator is shared across all channel circuits, and data streams are time-division multiplexed through the single CDR circuit, reducing the overall layout area while maintaining the ability to recover multiple data streams independently.
Solution Approach 2:
The single CDR circuit is designed to be universal and multi-functional, capable of processing different data streams with varying data rates. The sampling clock generator can be dynamically configured to handle different clock frequencies, and the CDR circuit can adapt to different data stream characteristics, making it a universal solution for multiple channel circuits.
2Reliability
If multiple CDR circuits are implemented for different data streams, then each data stream can be recovered independently, but operating power increases significantly
Solution Approach 1:
The patent merges multiple CDR circuits into a single shared CDR circuit that processes multiple data streams sequentially. By sharing the sampling clock generator and CDR processing resources across all channel circuits, the total operating power is significantly reduced compared to having separate CDR circuits for each data stream.
Solution Approach 2:
The single CDR circuit processes data streams using periodic time-division multiplexing, where each data stream is processed in alternating time slots. The sampling clock generator produces clocks at different frequencies periodically, allowing the CDR circuit to handle multiple data streams with varying rates by switching between them in a periodic manner, thus reducing overall power consumption.
3Area of stationary object
If a single CDR circuit is shared across multiple channel circuits, then layout area and power consumption are reduced, but the circuit must handle varying data rates efficiently
Solution Approach 1:
The sampling clock generator is designed to be dynamic and reconfigurable, capable of producing clock signals at different frequencies on demand. The clock generator can dynamically adjust its output frequency based on the data rate of the current data stream being processed, allowing the single CDR circuit to adapt to varying data rates across different channel circuits.
Solution Approach 2:
The system changes operational parameters (clock frequency, data stream selection) to handle different data rates. The sampling clock generator can change its output frequency parameter to match the data rate of the active data stream, and the CDR circuit adjusts its processing parameters accordingly, enabling a single circuit to handle multiple data rates effectively.
Data Source
AI summary
In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.