Multi-Phase Clock Generation with Phase Averaging for Low Jitter
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Solution Overview
Problem
Conventional multi-phase generating apparatuses for DLL circuits face challenges in maintaining equal phase differences between clock signals across varying frequencies, leading to reduced stability and increased jitter, especially in high-frequency operations, and difficulty in frequency locking at low frequencies.
Innovation Solution
A method and apparatus that generate L reference clock signal groups with predetermined phase delay intervals, averaging phases of sub reference clock signals to produce L main reference clock signals, which are then sequentially delayed to produce N multi-phase clock signals with reduced phase offsets, ensuring equal phase intervals regardless of the external clock signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the unit delay time of each delay cell is increased to achieve frequency locking at low operating frequencies, then frequency locking capability is improved, but jitter increases at high frequencies
Solution Approach 1:
The delay cell block is divided into multiple channels, each generating a subset of phase-shifted clock signals. This segmentation allows each channel to use shorter delay cells optimized for high-frequency operation, while collectively covering the full frequency range through parallel operation of multiple channels.
Solution Approach 2:
The invention transitions from a single-channel sequential delay approach to a multi-channel parallel architecture. By adding the channel dimension, the system achieves frequency locking capability without requiring long unit delay times, as each channel operates independently with optimized short delays.
2Adaptability or versatility
If the total delay time of delay cells is increased to achieve frequency locking, then frequency locking capability is improved, but phase offset increases reducing stability
Solution Approach 1:
The total phase shift requirement is segmented across multiple channels, each contributing a portion of the final multi-phase clock signals. This distribution reduces the cumulative phase offset in each individual channel while maintaining the overall frequency locking capability through parallel channel operation.
Solution Approach 2:
Multiple channels are merged to produce the final multi-phase clock signals. By combining the outputs of multiple channels with reduced individual phase offsets, the system achieves both frequency locking capability and improved phase stability through the collective contribution of all channels.
3Device complexity
If conventional multi-phase generating apparatus is used, then device complexity is reduced, but phase differences between clock signals become unequal at varying frequencies
Solution Approach 1:
The invention employs multiple channels with dynamically selectable delay cell configurations. Each channel can be independently optimized for different frequency ranges, allowing the system to maintain equal phase differences across varying frequencies by activating appropriate channel combinations based on the operating frequency.
Data Source
AI summary
A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for each reference clock signal group, and generating L main reference clock signals from the L×M sub reference clock signals; and sequentially delaying the L main reference clock signals, and generating the N multi-phase clock signals having the different phases. Because a plurality of clock signals having equal phase delay intervals between each other are generated regardless of the frequency of a received clock signal, the yield of Delay Locked Loop (DLL) circuits is improved using the multi-phase generating apparatus.