Multi-Phase Clock Generation With Feedback Phase Error Correction
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Solution Overview
Problem
Modern devices require faster data processing and higher data bandwidths, leading to increased power consumption, particularly in power-constrained devices like battery-powered devices.
Innovation Solution
A multi-phase clock generator system that receives an input clock signal and generates a multi-phase clock with N intermediate signals spaced approximately 360/N degrees apart in phase, using a poly phase filter and phase error corrector to reduce phase error and increase clock frequency without increasing input clock speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the input clock speed is increased to achieve faster data processing and higher data bandwidths, then the data processing speed and bandwidth are improved, but the power consumption increases significantly
Solution Approach 1:
The patent segments a single high-frequency clock signal into multiple lower-frequency clock signals with different phase offsets (e.g., 0°, 90°, 180°, 270°). This segmentation allows the system to achieve equivalent high-speed data processing functionality by combining multiple phase-shifted clock signals, thereby avoiding the need for a single high-frequency clock that would consume excessive power.
Solution Approach 2:
The patent introduces a phase dimension to the clock signal system. Instead of increasing frequency along the frequency dimension, the system uses multiple clock signals separated in the phase dimension. This dimensional transformation enables the system to achieve high-speed operation through phase diversity rather than frequency increase, thus reducing power consumption.
2Productivity
If the input clock speed is increased to achieve higher data bandwidths, then the data bandwidth is improved, but the power consumption increases significantly
Solution Approach 1:
The patent segments a single high-frequency clock signal into multiple lower-frequency clock signals with different phase offsets (e.g., 0°, 90°, 180°, 270°). This segmentation allows the system to achieve equivalent high-speed data processing functionality by combining multiple phase-shifted clock signals, thereby avoiding the need for a single high-frequency clock that would consume excessive power.
Solution Approach 2:
The patent introduces a phase dimension to the clock signal system. Instead of increasing frequency along the frequency dimension, the system uses multiple clock signals separated in the phase dimension. This dimensional transformation enables the system to achieve high-speed operation through phase diversity rather than frequency increase, thus reducing power consumption.
3Speed
If multi-phase clock signals are generated using traditional methods, then higher frequency clock signals can be achieved, but the phase error among the generated signals increases
Solution Approach 1:
The patent employs a feedback mechanism where a phase detector continuously monitors the phase relationships among the generated clock signals and provides feedback to a phase adjustor. This closed-loop control system dynamically corrects phase errors, ensuring that the generated multi-phase clock signals maintain high frequency while preserving accurate phase relationships.
Solution Approach 2:
The patent introduces a phase adjustor as an intermediary component between the clock signal generator and the output stage. This intermediary actively compensates for phase errors by adjusting the phase of individual clock signals based on feedback from the phase detector, thereby maintaining high frequency operation with precise phase accuracy.
Data Source
AI summary
Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.