Multi-Phase Clock Mixing to Reduce Phase Error Accumulation
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Solution Overview
Problem
Multi-phase clock generation circuits face phase error accumulation due to random mismatch of circuit elements, leading to uncertainty in clock signal phases and limited operating frequencies, which existing solutions attempt to mitigate by increasing transistor size and current, resulting in undesirable device size and power consumption.
Innovation Solution
The proposed multi-phase clock generation circuit employs clock mixer circuits with differential amplifiers that average multiple clock phase input signals to reduce relative phase error, utilizing a delay-locked loop and clock mixer configurations to minimize phase error without increasing transistor size or current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor size and current are increased to reduce phase error, then phase error is reduced, but device size and power consumption increase
Solution Approach 1:
The patent combines multiple clock phases (e.g., five phases) into a single averaged clock phase using clock mixer circuits. By merging the signals and averaging them, the phase errors from random mismatch are reduced without requiring larger transistors or higher currents, thus resolving the contradiction between phase error reduction and power consumption.
2Measurement precision
If transistor size and current are increased to reduce phase error, then phase error is reduced, but device size increases
Solution Approach 1:
The patent merges multiple clock phases through clock mixer circuits to average out phase errors. This approach reduces phase error without requiring larger individual transistors, thereby reducing the overall device area while maintaining or improving phase accuracy.
3Productivity
If clock phases are generated using traditional delay circuits, then clock signal is produced, but phase error accumulates across multiple phases
Solution Approach 1:
The patent implements a feedback mechanism where the averaged clock phase is fed back to adjust the delay elements in the delay-locked loop. This feedback continuously corrects accumulated phase errors, maintaining high phase accuracy across multiple clock phases while enabling continuous clock signal generation.
Solution Approach 2:
The patent combines multiple clock phases using clock mixer circuits that average the signals. This merging process reduces the accumulated phase errors that would otherwise occur in traditional sequential delay circuits, while still enabling continuous clock signal production.
Data Source
AI summary
A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.