Multi-Phase Clock Generation With Phase Error Feedback
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Solution Overview
Problem
Modern devices, particularly power-constrained devices like battery-powered communication devices, face significant power consumption issues due to high-speed data processing and communication demands, which are exacerbated by high-speed clocks and oscillators.
Innovation Solution
A multi-phase clock generator system that receives an input clock signal and generates N intermediate signals spaced approximately 360/N degrees apart in phase, using a poly phase filter and phase error corrector to produce clock output signals with reduced phase error, allowing for higher frequency operations without increasing input clock speed, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed clocks and oscillators are used to achieve faster data processing and higher data bandwidths, then productivity is improved, but use of energy worsens
Solution Approach 1:
The patent divides a single high-frequency clock signal into multiple lower-frequency clock signals with different phases (e.g., 0°, 90°, 180°, 270°) using a polyphase filter. This segmentation allows the system to achieve high-speed data processing through parallel processing with multiple phase-shifted clocks while each clock operates at a lower frequency, thereby reducing power consumption compared to using a single high-frequency clock.
2Productivity
If the input clock speed is increased to enable higher frequency operations, then productivity is improved, but use of energy worsens
Solution Approach 1:
The patent transitions from a single-dimensional approach (one high-frequency clock) to a multi-dimensional approach by generating multiple clock signals with different phase dimensions. The polyphase filter creates N clock outputs from a single input clock, where each output has a distinct phase angle (360/N degrees apart). This dimensional expansion in phase space enables high-frequency operations through parallel processing without requiring the input clock to run at higher speeds, thus avoiding the associated power consumption increase.
3Manufacturing precision
If multi-phase clock signals are generated using polyphase filter and phase error corrector, then manufacturing precision is improved, but device complexity worsens
Solution Approach 1:
The patent incorporates a feedback mechanism through the phase error corrector, which receives the N clock outputs from the polyphase filter, detects phase errors in each clock signal, and generates correction signals to adjust the phase of each clock output. This feedback loop automatically corrects phase deviations, ensuring precise phase relationships (360/N degrees apart) without requiring manual calibration or complex external testing equipment, thereby achieving high manufacturing precision despite the increased device complexity.
Data Source
AI summary
Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.