Multiphase Clock Circuit with PLL Feedback for Precise Pulse Widths

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Solution Overview

Problem

Existing multiphase clock generation circuits face challenges in precisely controlling the frequency of multiphase clock signals to correct variations in lens characteristics in laser beam printers, leading to inaccuracies in pulse width and position of printing areas.

Innovation Solution

A multiphase clock generation circuit incorporating a phase-locked loop, frequency profile holding circuit, and clock selection circuit, which allows for arbitrary phase selection and frequency profile updates, enabling precise control of multiphase clock signal frequencies and pulse widths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the frequency of the multiphase clock signal is changed to correct lens characteristics, then printing quality is improved, but the control precision of the clock frequency is insufficient

Engineering Contradiction:
Improveprinting qualityVSAvoidclock frequency control precision
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent segments the continuous frequency adjustment range into discrete frequency steps corresponding to different phase selections. By dividing the frequency control into quantized levels based on phase selection, the system achieves precise frequency control through the frequency control circuit that switches between predetermined frequency values associated with each phase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the frequency parameter of the multiphase clock signal based on the selected phase. The frequency control circuit dynamically adjusts the clock frequency to predetermined values corresponding to different phase selections, enabling precise frequency control that adapts to lens characteristics while maintaining synchronization.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a delay-locked loop is used to generate multiphase clock signals, then the circuit structure is simplified, but the frequency control precision is insufficient to correct lens variations

Engineering Contradiction:
Improvecircuit structureVSAvoidfrequency control precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces a feedback mechanism where the phase selection result is fed back to the frequency control circuit. The frequency control circuit uses this feedback to automatically adjust the clock frequency to predetermined values corresponding to the selected phase, creating a closed-loop control system that achieves high precision frequency control without significantly increasing circuit complexity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the frequency control dynamic by linking it to the phase selection process. Instead of using a fixed frequency, the system dynamically adjusts the clock frequency based on which phase is selected, allowing the frequency to adapt in real-time to correct lens variations while maintaining a relatively simple circuit structure.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for high-precision control of multiphase clock signal frequencies and pulse widths, improving printing quality by accurately adjusting for lens variations, even with low-precision lenses.

Implementation Method 1

a phase-locked loop circuit for generating multiphase clock signals based on a reference clock signal

Methodology Applied
Scientific EffectPhase-locked loop:

Data Source

PatentUS7683690B2Multiphase clock generation circuit
Publication Date: 2010.03.23 RENESAS ELECTRONICS CORP
  • US7683690B2 patent drawing
  • US7683690B2 patent drawing
  • US7683690B2 patent drawing

AI summary

Provided is a multiphase clock generation circuit (1) including: a phase-locked loop circuit (10) for generating multiphase clock signals based on a reference clock signal; a frequency profile holding circuit (20) for holding a frequency profile of each of the multiphase clock signals, starting output of the frequency profile in response to a start signal, and for updating the frequency profile with a predetermined cycle based on the reference clock signal; and a clock selection circuit (30) for selecting a clock signal with an arbitrary phase from among the multiphase clock signals based on the frequency profile, and for feeding back the selected clock signal to the phase-locked loop circuit (10).