Open-Loop Multiphase Clock Generator for PVT-Stable Phase Control
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Solution Overview
Problem
Conventional frequency synthesizers rely on closed-loop PLL or DLL circuits, which can be complex and prone to variations in process, voltage, and temperature, affecting the accuracy and stability of multiphase clock generation.
Innovation Solution
An open-loop multiphase clock generator utilizing a current mirror, voltage controller, pseudo-resistor circuit, and delaying circuits to generate multiple clock signals with precise phase differences, independent of process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional closed-loop PLL or DLL circuits are used for frequency synthesis, then frequency multiplication and phase control functions are achieved, but circuit complexity increases and susceptibility to process, voltage, and temperature variations worsens
Solution Approach 1:
The patent inverts the conventional approach by using an open-loop architecture instead of closed-loop PLL/DLL. The frequency synthesizer directly generates output clocks from reference clocks through parallel delay paths without feedback control, eliminating the complexity of phase detectors, charge pumps, and loop filters while maintaining frequency synthesis functionality through controlled delay elements.
Solution Approach 2:
The patent segments the frequency synthesis function into multiple parallel delay paths, each generating a specific phase-shifted clock signal. By dividing the output clock into multiple branches with controlled delay elements, the system achieves multiphase clock generation without requiring complex closed-loop control mechanisms, thereby reducing circuit complexity.
2Measurement precision
If closed-loop PLL circuits are used for multiphase clock generation, then phase control capability is achieved, but accuracy and stability deteriorate due to PVT variations
Solution Approach 1:
The patent uses copying by replicating delay path structures in parallel, where each path is designed to produce a specific phase shift. By copying the delay element designs and configuring them with controlled delay values, the system achieves accurate phase differences that are insensitive to PVT variations, as each copied path experiences similar environmental conditions.
Solution Approach 2:
The patent changes the delay parameter of each parallel path to achieve different phase shifts. By controlling the delay values (e.g., through transistor width ratios or capacitor sizes) in each path, the system precisely sets phase differences between output clocks while maintaining stability against PVT variations through open-loop design.
3Device complexity
If open-loop architecture is used for frequency synthesis, then circuit complexity is reduced, but control precision over phase differences must be maintained
Solution Approach 1:
The patent introduces dynamic control capability by making delay elements adjustable through control signals. The delay amount in each parallel path can be dynamically changed by adjusting control voltages or currents, allowing precise phase difference control while maintaining the simplicity of open-loop architecture. This dynamic adjustment compensates for any manufacturing variations.
Solution Approach 2:
The patent replaces physical/mechanical phase control mechanisms (such as mechanical switches or variable capacitors) with electronic control methods using transistors and capacitors in integrated circuits. The delay elements are controlled through electrical parameters (transistor widths, capacitor sizes, control voltages), enabling precise phase control without mechanical complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables accurate control of delaying time and phase differences between clock signals, ensuring stable and temperature-independent output clock frequencies, improving the reliability of multiphase clock generation.
Implementation Method 1
a current mirror including a receiving terminal, a first mirroring terminal and a second mirroring terminal
Implementation Method 2
The pseudo-resistor circuit includes a first capacitor, a first switch, a second switch, a third switch and a fourth switch
Data Source
AI summary
A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.


