Multi-Phase Clock Recovery for Jitter-Tolerant Fast Phase Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock and data recovery circuits (CDRs) face issues with high jitter tolerance and slow phase locking, leading to errors and initial locking delays in high-speed serial communication systems.
Innovation Solution
A clock and data recovery circuit that includes a phase sampler module, a phase adjust module, and a phase select module to sample clock phase signals on data input signal edges, evaluate timing relationships, and produce a clock output signal for accurate data recovery, with the ability to handle large instantaneous timing jitter and quickly lock to new data inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior CDR designs are used, then the circuit can recover data from serial communication links, but the circuit produces errors under large instantaneous timing jitter conditions
Solution Approach 1:
The CDR circuit segments the clock signal into multiple phase-shifted clock signals (e.g., 2, 4, or more phases equally spaced in phase). The phase detector then evaluates which phase provides the best timing alignment with the data transitions, allowing the circuit to tolerate large instantaneous timing jitter by selecting the optimal phase segment.
Solution Approach 2:
The circuit dynamically selects among multiple clock phases based on real-time evaluation of timing relationships. The phase detector continuously monitors data transitions and adjusts the selected clock phase to match the optimal timing point, enabling adaptive response to varying jitter conditions.
2Reliability
If prior CDR designs are used, then the circuit can operate with clock phase signals, but the circuit exhibits slow initial locking to the input data
Solution Approach 1:
The circuit generates multiple clock phase signals in advance before data recovery begins. During the initial locking phase, the phase detector evaluates these pre-generated phases against incoming data transitions and quickly identifies the optimal phase, significantly reducing initial locking time compared to circuits that generate clock phases sequentially or reactively.
Solution Approach 2:
The phase detector provides immediate feedback by evaluating sampled clock phase values against data transitions and selecting the phase with the best timing alignment. This feedback mechanism enables fast initial locking by continuously monitoring and adjusting the selected phase based on real-time timing relationship evaluation.
3Object-affected harmful factors
If complex circuitry is added to handle timing jitter, then jitter tolerance improves, but the device complexity increases
Solution Approach 1:
Instead of using complex continuous-time jitter compensation circuits, the invention segments the clock signal into discrete phase segments. This allows jitter tolerance to be achieved through simple phase selection logic rather than complex analog processing, reducing overall circuit complexity while maintaining high jitter tolerance.
Solution Approach 2:
The phase detector acts as an intermediary that evaluates timing relationships between data transitions and clock phases, selecting the optimal phase without requiring complex jitter measurement and compensation circuits. This intermediary approach simplifies the overall circuit architecture by replacing complex continuous-time processing with discrete phase evaluation and selection.
Data Source
AI summary
Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.