Multi-Phase Clock De-Skewing With Reference Event Comparison
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Solution Overview
Problem
Existing multi-phase clock systems are limited by their inability to operate accurately at high frequencies due to difficulties in measuring and calibrating short time intervals between clock phases, leading to a maximum operational clock frequency constraint.
Innovation Solution
A multi-phase clock system that uses a reference clock signal with a different frequency to determine desired time events, allowing for sequential comparison and de-skewing of clock signals, thereby eliminating the need for precise measurement of short time intervals and enabling operation at higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-phase clock system uses continuous measurement of short time intervals between clock phases for skew calibration, then phase accuracy can be maintained, but the maximum operational clock frequency is limited due to measurement difficulties at high frequencies
Solution Approach 1:
The patent introduces an intermediary measurement process where time intervals between clock phases are measured against a reference clock signal with a lower frequency. This intermediary reference clock acts as a mediator that enables accurate measurement of high-frequency clock phases by comparing them to a slower, more easily measurable reference signal, thereby resolving the contradiction between maintaining phase accuracy and operating at high frequencies
Solution Approach 2:
The system performs self-calibration by automatically measuring its own clock phase intervals and adjusting skew without external intervention. The multi-phase clock system uses its own reference clock signal to measure and correct its phase relationships, enabling continuous self-optimization of phase accuracy regardless of operating frequency
2Measurement precision
If a multi-phase clock system uses a high frequency clock divided down to lower frequency with many phases, then phase accuracy is acceptable, but power consumption increases due to many high-speed dividers and retiming flip-flops
Solution Approach 1:
Instead of dividing a high-frequency clock down to generate multiple phases (which consumes high power), the patent inverts the approach by using a lower frequency reference clock and generating the multi-phase signals from there. This inversion eliminates the need for power-hungry high-speed dividers and retiming flip-flops while maintaining acceptable phase accuracy
3Speed
If a multi-phase ring oscillator is used to produce clock phases at very high frequencies, then speed is improved, but timing error accumulation increases due to errors in producing a large number of phases
Solution Approach 1:
The patent implements feedback by continuously measuring the actual time intervals between clock phases using the reference clock and comparing them against ideal intervals. The system then uses this feedback information to correct skew and compensate for timing errors, preventing error accumulation even at very high frequencies where ring oscillators operate
Data Source
AI summary
The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).