Multiphase Clock Calibration for Fast PLL Sampling Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ethernet network reception ends face challenges in rapidly re-establishing optimal sampling clocks after power-saving mode, leading to sampling errors due to potential incorrect clock outputs from restarted phase lock loops, which consumes time and reduces power-saving effectiveness.
Innovation Solution
A phase calibration device and method that includes an oscillator, phase lock loop, multiphase clock generator, selector, analog-to-digital converter, and control circuit to rapidly determine and adjust the optimal sampling clock, using a calibration signal and stored parameters to ensure correct clock selection even after power-saving mode, by regenerating clocks based on a stable reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the phase lock loop is shut down to save power, then power consumption is reduced, but sampling errors occur due to incorrect clock output after restart
Solution Approach 1:
The patent applies preliminary action by performing phase calibration before the phase lock loop is shut down, storing the calibration results. When the loop restarts, these pre-stored calibration results enable rapid recovery without requiring full recalibration, thus maintaining sampling accuracy while achieving power savings.
Solution Approach 2:
The patent uses feedback mechanisms where the system continuously monitors sampling quality and automatically triggers phase calibration when degradation is detected. This closed-loop feedback ensures sampling accuracy is maintained while allowing the phase lock loop to be shut down during normal operation to save power.
2Speed
If the phase lock loop is restarted quickly to maintain operation, then response time is reduced, but sampling errors occur due to incorrect clock output
Solution Approach 1:
The system performs phase calibration in advance and stores the results before shutting down the phase lock loop. Upon restart, these pre-computed calibration values enable immediate resumption of accurate operation, achieving both fast response time and high reliability.
Solution Approach 2:
The patent creates a copy of the calibration state and stores it in memory. When the phase lock loop restarts, this stored copy is rapidly loaded and applied, avoiding the need to perform time-consuming calibration procedures from scratch, thus maintaining both speed and accuracy.
3Reliability
If repeated clock selection is performed after power-saving mode, then sampling accuracy is restored, but time is consumed and power-saving effect is reduced
Solution Approach 1:
The system performs phase calibration before entering power-saving mode and stores the calibration results. Upon exiting power-saving mode, the stored calibration data is rapidly applied, eliminating the need for repeated time-consuming calibration cycles and reducing both time loss and maintaining power-saving effectiveness.
Solution Approach 2:
The calibration state is copied and stored in memory before shutdown. When resuming operation, this copy is instantly restored and applied, avoiding repeated calibration processes and significantly reducing the time required to restore sampling accuracy while preserving power-saving benefits.
Data Source
AI summary
A phase calibration device comprises: an oscillator for generating a reference clock; a phase-lock-loop for generating an input clock by the reference clock; a multiphase clock generator for generating a plurality of output clocks by the input clock; a selector for selecting one of the output clocks as an operation clock; an analog-to-digital convertor for performing analog-to-digital conversion to input data by the operation clock to generate a conversion result; a control circuit for generating parameters according to the conversion result and controlling the selector to do selection; and a phase calibration circuit for outputting a calibration signal and the input clock of the phase-lock-loop to the multiphase clock generator after restarting the phase-lock-loop, so that the multiphase clock generator can correctly regenerate the output clocks by the calibration signal and the input clock, and then the control circuit controls the selector to do selection by the parameters.