Multiphase Clock Self-Test Circuit for Flip-Flop Defect Detection
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Solution Overview
Problem
Conventional self-test circuits for digital circuits face challenges in detecting defects at the highest clock speed without switching operation modes or reducing clock speed, leading to ambiguous testing and difficulties in timing adjustment.
Innovation Solution
A self-test circuit driven by a multiphase clock signal with N phases, incorporating a data selecting circuit, serialization circuit, and logical test circuit, allowing for serial conversion and bit-level testing of flip-flops without mode switching or speed reduction, ensuring accurate defect detection and reliable clock control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock or selector is added to switch from normal operation mode to scan test mode, then defect detection capability is improved, but timing adjustment becomes difficult and device complexity increases
Solution Approach 1:
The patent applies multi-functionality by enabling the existing clock and selector circuits to serve dual purposes: normal operation mode and scan test mode. The clock signal and selector are configured to operate in both modes without requiring additional dedicated test-mode components, thereby achieving defect detection capability while avoiding increased device complexity.
2Measurement precision
If test is performed at highest clock speed, then timing adjustment verification is improved, but mode switching requirements increase complexity
Solution Approach 1:
The patent enables the test circuit to verify timing adjustment at the highest clock speed by configuring the existing mode-switching infrastructure to support both normal operation and scan test modes. This approach allows timing verification at maximum speed without requiring separate dedicated test mode circuits, thereby maintaining measurement precision while avoiding additional complexity.
3Reliability
If clock speed is reduced for testing, then defect detection becomes possible, but testing accuracy at highest clock speed deteriorates
Solution Approach 1:
The patent applies dynamics by enabling the test circuit to operate at the highest clock speed dynamically, rather than requiring reduced clock speed for testing. The mode switching mechanism is configured to allow scan test operation at maximum clock frequency, thereby maintaining both defect detection capability and timing verification accuracy simultaneously.
4Reliability
If mode switching is implemented for scan test, then defect detection is enabled, but timing adjustment difficulty increases
Solution Approach 1:
The patent applies universality by configuring the clock and selector circuits to serve both normal operation and scan test functions. This dual-mode configuration allows defect detection to be enabled while maintaining ease of timing adjustment, as the same circuits are used in both modes and can be synchronized using the existing timing adjustment mechanisms.
Data Source
AI summary
A self-test circuit is driven by a multiphase clock signal which includes N number of clock signals in same cycle having phases from first to N-th phases each phase-shifted by 1/N of the cycle. The self-test circuit includes a data selecting circuit, a serialization circuit, and a logical test circuit. The data selecting circuit switches input data that are input as M-bit wide parallel data to the self-test circuit, between normal data and test data for logical test. The serialization circuit performs serial conversion of the input data in N-parallel manner and outputs bits in N-parallel manner, as a single serial output signal at timing corresponding to each phase. In synchronization with timing corresponding to each phase, the logical test circuit imports the serial output signal as N-parallel bit strings each having length equal to M/N number of bits and performs a bit logical test for M number of bits.