Multiphase Clock Generation with Local Skew Correction
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Solution Overview
Problem
Conventional clock generation methods in integrated circuits require high power consumption, large die area, and are susceptible to noise and phase skew due to the use of divide-by-two circuits and extensive distribution networks for quadrature clock phases, which degrades signal-to-noise ratio and bit-error rate in high-speed data converters and SerDes macros.
Innovation Solution
A multi-phase clock generation system that centrally generates two clock phases at the target frequency without a divide-by-two circuit and locally generates the remaining phases using multi-phase generator (MPG) circuits, reducing power consumption and die area, and incorporating skew-correction and amplitude-correction loops to maintain phase accuracy and reduce noise susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a divide-by-two circuit is used to generate clock phases from a higher frequency source, then the clock frequency can be doubled, but power consumption and die area increase
Solution Approach 1:
The clock generation system is divided into a central PLL that generates two phases and local MPG circuits that generate the remaining phases. This segmentation eliminates the need for a divide-by-two circuit while distributing the generation function, reducing power consumption and die area compared to a centralized high-frequency source approach.
Solution Approach 2:
The patent transitions from a single centralized clock source operating at twice the target frequency to a distributed architecture where multiple clock sources operate at the target frequency. This dimensional change in system architecture eliminates the divide-by-two circuit requirement and reduces power consumption.
2Stability of the object's composition
If a centralized distribution network is used to deliver all four clock phases to all lanes, then clock synchronization is simplified, but die area and power consumption increase
Solution Approach 1:
The clock distribution function is segmented between central PLL circuits that generate reference phases and local MPG circuits that generate additional phases. This reduces the distribution network scope from four phases across the entire chip to two phases locally, decreasing die area while maintaining synchronization through phase-matched local generation.
Solution Approach 2:
Each lane or lane group is equipped with local MPG circuits that generate clock phases locally rather than receiving all phases from a central source. This local generation approach reduces the burden on the central distribution network, decreasing die area while maintaining clock quality through localized phase generation.
3Length of stationary object
If MPG circuits drive large interconnects, then clock signals can be distributed to all lanes, but inductors are required for resonance and magnetic coupling with other circuits occurs
Solution Approach 1:
The clock distribution is segmented into local domains where MPG circuits drive only local interconnects to nearby PIs rather than long interconnects across the entire chip. This segmentation eliminates the need for large inductors and reduces magnetic coupling with other circuits while maintaining adequate clock signal distribution.
Solution Approach 2:
MPG circuits are designed to drive only local interconnects with limited length rather than long global interconnects. This local approach eliminates the requirement for inductors and prevents magnetic coupling issues while still providing clock signals to all necessary lanes through the distributed architecture.
4Measurement precision
If error-sensing circuits are added to sense and adjust clock phase skew and amplitude error, then phase accuracy is improved, but power consumption and area increase
Solution Approach 1:
Error-sensing circuits are implemented to detect phase skew and amplitude errors in the generated clock phases, with feedback loops that automatically adjust the MPG circuits to correct these errors. This feedback mechanism improves phase accuracy while the circuits are designed to minimize power consumption and area overhead.
Solution Approach 2:
The MPG circuits incorporate self-correction capabilities through integrated error-sensing and feedback mechanisms that automatically adjust their own operation to maintain accurate phase relationships. This self-service approach improves phase accuracy without requiring external correction circuits, minimizing additional power consumption and area.
Data Source
AI summary
Systems and methods are disclosed for a multiphase clock generation. An example method includes facilitating, by a phase interpolator (PI) circuit comprising a plurality of PIs, transfer of information across one or both of a transmit (TX) lane or a receive (RX) lane, wherein the transfer of information is based on a clock timing. The PI circuit receives, from a clock-and-data recovery (CDR) circuit, a plurality of input clock phases. The CDR circuit comprises a centrally located phase-locked loop (PLL) circuit and a plurality of multiphase generators. In some embodiments, each multiphase generator of the plurality of multiphase generators is adjacent to a respective PI of the plurality of PIs. Based on the plurality of input clock phases, the PI circuit adjusts, the clock timing for the transfer of information.